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nate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8a879141dcd15d2db876ce3adf88b9b01650b7fa'/> urn:sha1:8a879141dcd15d2db876ce3adf88b9b01650b7fa Using the correct bit helps. The documentation specifies bit 0 in both registers to be controlling polarity of dpi_vsync_input and dpi_hsync_input polarity. Bit 1 is reserved, and should therefore not be set. Tested with panel that requires active high vsync and hsync. Signed-off-by: Esben Haabendal <esben@geanix.com> Reviewed-by: Robert Foss <rfoss@kernel.org> Signed-off-by: Robert Foss <rfoss@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240814-nwl-dsi-sync-polarity-v1-1-ee198e369196@geanix.com