Documentation/CodingStyle


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This file has moved to process/coding-style.rst
Age	Commit message (Expand)	Author
2011-10-18	m68knommu: create common externs for _ram* vars	Greg Ungerer
2011-10-18	m68knommu: remove extern declarations of memory_start/memory_end from mm/init	Greg Ungerer
2011-10-18	m68knommu: use generic section names in mm/init code	Greg Ungerer
2011-07-25	m68knommu: Fix printk() format in free_initrd_mem()	Geert Uytterhoeven
2011-07-25	m68knommu: Make empty_zero_page "void *", like on m68k	Geert Uytterhoeven
2011-05-24	m68knommu: clean up mm/init_no.c	Greg Ungerer
2011-03-25	m68k: merge m68k and m68knommu arch directories	Greg Ungerer
2025-10-27	clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules	Lad Prabhakar
	Add clock and reset definitions required to support the DSI and LCDC hardware blocks on the RZ/V2N SoC. This includes new core clocks, clock dividers, module clocks, and reset entries, as well as PLL and divider configurations specific to these peripherals. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251023210724.666476-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-09-12	clk: renesas: r9a09g05[67]: Reduce differences	Geert Uytterhoeven
	The clock drivers for RZ/V2H and RZ/V2N are very similar. Reduce the differences between them by: - Moving and reformatting the PLLCM33_GEAR clock definitions, - Replacing spaces by TABs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/2246d2263e8a24d1aaf653db2004cbf2263c9048.1757606097.git.geert+renesas@glider.be
2025-09-11	clk: renesas: r9a09g056: Add clock and reset entries for I3C	Lad Prabhakar
	Add module clock entries for the I3C controller on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20250904155507.245744-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02	clk: renesas: r9a09g056: Add XSPI clock/reset	Lad Prabhakar
	Add XSPI clock and reset entries. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250627204237.214635-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02	clk: renesas: r9a09g056: Add support for xspi mux and divider	Lad Prabhakar
	The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and pllcm33_xspi divider to select different clock rates. Add support for both. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250627204237.214635-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10	clk: renesas: r9a09g056: Add clock and reset entries for USB2.0	Lad Prabhakar
	Add clock and reset entries for USB2.0. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250528132558.167178-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10	clk: renesas: r9a09g056: Add clocks and resets for Mali-G31 GPU	Lad Prabhakar
	Add clock and reset support for the Mali-G31 GPU on the Renesas RZ/V2N (R9A09G056) SoC. This includes adding clock sources required for the module clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10	clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers	Lad Prabhakar
	Add module clock and reset definitions for WDT0-3, which are available on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10	clk: renesas: r9a09g056: Add clock and reset entries for RIIC controllers	Lad Prabhakar
	Add module clock and reset definitions for RIIC controllers 0-8, which are available on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10	clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instances	Lad Prabhakar
	Introduce a new fixed divider .pllcln_div16 which is sourced from PLLCLN and add PCLK module clocks gtm_0_pclk through gtm_7_pclk for OSTM0-7. Add corresponding reset lines GTM_0_PRESETZ through GTM_7_PRESETZ to control the OSTM instances. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10	clk: renesas: r9a09g056-cpg: Add clock and reset entries for GBETH0/1	Lad Prabhakar
	Add clock and reset entries for GBETH instances. Include core clocks for PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks used as clock sources for the GBETH IP. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14	clk: renesas: rzv2h: Add support for RZ/V2N SoC	Lad Prabhakar
	The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present only on the RZ/V2H(P) SoC. Add minimal clock and reset entries required to boot the Renesas RZ/V2N EVK and binds it with the RZ/V2H CPG family driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>