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c1a9c67ed7de775'>clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu 2019-04-11clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen 2019-04-11clk: mediatek: Disable tuner_en before change PLL rateOwen Chen 2017-11-02clk: mediatek: add the option for determining PLL source clockChen Zhong 2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com