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generated by cgit v1.2.3 (git 2.46.0) at 2026-07-23 22:28:05 +0000
ERR_PTR(...) ) ; // Fix pointer usage @@ identifier CD; expression E; @@ - CD->clks[E] + CD->hws[E] // Fix mtk_clk_pll_get_base() @@ symbol clk, hw, data; @@ mtk_clk_pll_get_base( - struct clk *clk, + struct clk_hw *hw, const struct mtk_pll_data *data ) { - struct clk_hw *hw = __clk_get_hw(clk); ... } // Fix mtk_clk_pll_get_base() usage @@ identifier CD; expression E; @@ mtk_clk_pll_get_base( - CD->clks[E] + CD->hws[E]->clk ,... ); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-4-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> clk: mediatek: use en_mask as a pure div_en_mask 2022-05-19T00:42:22Z Chun-Jie Chen chun-jie.chen@mediatek.com 2022-05-13T07:36:21Z urn:sha1:e1fd35f5cdffea714f7a285a1eb68863c72acb4e We no longer allow en_mask to be a combination of pll_en_bit and div_en_mask, so remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask that only used for pll dividers. This commit continues the work done in commit 7cc4e1bbe300 ("clk: mediatek: Fix asymmetrical PLL enable and disable control") and commit f384c44754b7 ("clk: mediatek: Add configurable enable control to mtk_pll_data") to clean up en_mask(bit0) default setting. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com> Link: https://lore.kernel.org/r/20220513073621.12923-1-mandyjh.liu@mediatek.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>