diff options
| author | Dave Jiang <dave.jiang@intel.com> | 2025-03-14 16:22:34 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-03-14 16:22:34 -0700 |
| commit | 763e15d04740ad2984bf009d9a5f70c099c8e6fd (patch) | |
| tree | d1d2e70d4ac33eb687d9a863684e03aad0be4d18 /tools/testing/cxl | |
| parent | d781a45270a8acabe2576cc5c47dc33180eca87c (diff) | |
| parent | 516e5bd0b6bf4ae1ad072df637b428a737c3c870 (diff) | |
Merge branch 'for-6.15/extended-linear-cache' into cxl-for-next2
Add support for Extended Linear Cache for CXL. Add enumeration support
of the cache. Add MCE notification of the aliased memory address.
Diffstat (limited to 'tools/testing/cxl')
| -rw-r--r-- | tools/testing/cxl/Kbuild | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 3d71447c0bd8..a7ec67d4a0f2 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -62,8 +62,10 @@ cxl_core-y += $(CXL_CORE_SRC)/hdm.o cxl_core-y += $(CXL_CORE_SRC)/pmu.o cxl_core-y += $(CXL_CORE_SRC)/cdat.o cxl_core-y += $(CXL_CORE_SRC)/ras.o +cxl_core-y += $(CXL_CORE_SRC)/acpi.o cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o +cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o cxl_core-y += config_check.o cxl_core-y += cxl_core_test.o cxl_core-y += cxl_core_exports.o |