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| author | Dinh Nguyen <dinguyen@altera.com> | 2014-02-19 14:56:38 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@altera.com> | 2014-03-02 14:58:08 -0600 |
| commit | f1ce1a99f289474cf047923981369d5ba140c125 (patch) | |
| tree | aa2f3c7f5502f37dc4e9b196d965cec2180d1808 /tools/perf/scripts/python | |
| parent | 73960387b22dfb3f9088852cc41f1a995cd0b502 (diff) | |
| download | kernel-f1ce1a99f289474cf047923981369d5ba140c125.tar.gz | |
dts: socfpga: Update clock entry to support multiple parents
The periph_pll and sdram_pll can have multiple parents. Update the device tree
to list all the possible parents for the PLLs. Add an entry for the the
f2s_sdram_ref_clk, which is a possible parent for the sdram_pll.
Also remove the clock-frequency entry in the f2s_periph_ref_clk, as this
property should be placed in dts file.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions