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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-12-09 21:28:28 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-10 17:47:24 +0100 |
| commit | eb736679aa7e6d6de647909fdf13075605927b3a (patch) | |
| tree | 63c13fa2b5d6072bcd4e58ef522458e23db8616b /tools/perf/scripts/python | |
| parent | 16e5ab14d7828c461c346e78f9ba1e9bdd0257aa (diff) | |
| download | kernel-eb736679aa7e6d6de647909fdf13075605927b3a.tar.gz | |
drm/i915: Engage the DP scramble reset for pipe C on CHV
To get stable CRCs from the DP CRC source we need to reset the
scrambler for each frame. Enable the reset feature when grabbing
CRCs for pipe C on CHV. Pipes A and B were already covered due
sharing the code with VLV.
We can safely extend PIPE_SCRAMBLE_RESET_MASK to deal with CHV since
the extra bit was MBZ on the older platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions