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| author | Jan Kotas <jank@cadence.com> | 2019-07-22 04:22:22 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-07-25 06:43:01 -0400 |
| commit | 6ded416d4ac4ecbf104b897661cdfa2cdacf022a (patch) | |
| tree | 963e756610e111613fb267be99ba0f7e1fdc68bd /tools/perf/scripts/python | |
| parent | bf9df90b3557ec6d5d92914da6a61453741d3e13 (diff) | |
| download | kernel-6ded416d4ac4ecbf104b897661cdfa2cdacf022a.tar.gz | |
media: Fix Lane mapping in Cadence CSI2TX
This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.
Signed-off-by: Jan Kotas <jank@cadence.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions