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authorDave Chinner <dchinner@redhat.com>2010-09-22 10:47:20 +1000
committerAlex Elder <aelder@sgi.com>2010-10-18 15:07:44 -0500
commite176579e70118ed7cfdb60f963628fe0ca771f3d (patch)
treee2d252fcd692aa4e3907300521e2af81c974f875 /tools/perf/scripts/python/stackcollapse.py
parentbd32d25a7cf7242512e77e70bab63df4402ab91c (diff)
downloadkernel-e176579e70118ed7cfdb60f963628fe0ca771f3d.tar.gz
xfs: lockless per-ag lookups
When we start taking a reference to the per-ag for every cached buffer in the system, kernel lockstat profiling on an 8-way create workload shows the mp->m_perag_lock has higher acquisition rates than the inode lock and has significantly more contention. That is, it becomes the highest contended lock in the system. The perag lookup is trivial to convert to lock-less RCU lookups because perag structures never go away. Hence the only thing we need to protect against is tree structure changes during a grow. This can be done simply by replacing the locking in xfs_perag_get() with RCU read locking. This removes the mp->m_perag_lock completely from this path. Signed-off-by: Dave Chinner <dchinner@redhat.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Alex Elder <aelder@sgi.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
1fc22183c52f786f6'>Merge tag 'tty-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gre...Linus Torvalds 2024-05-04arm64: zynqmp: Add resets property for UART nodesManikanta Guntupalli 2024-04-29arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usageRob Herring 2024-01-22arm64: zynqmp: Align usb clock nodes with bindingMichal Simek 2024-01-22arm64: zynqmp: Comment all smmu entriesMichal Simek 2024-01-22arm64: zynqmp: Introduce u-boot options node with bootscr-addressMichal Simek 2024-01-22arm64: zynqmp: Update ECAM size to discover up to 256 busesThippeswamy Havalige 2024-01-22arm64: zynqmp: Add resets property for CAN nodesSrinivas Neeli 2024-01-22arm64: zynqmp: Add an OP-TEE node to the device treeIlias Apalodimas 2024-01-22arm64: zynqmp: Rename zynqmp-power node to power-managementMichal Simek 2023-12-13arm64: zynqmp: Add missing destination mailbox compatibleMichal Simek 2023-12-13arm64: xilinx: Remove address/size-cells from gem nodesMichal Simek 2023-12-13arm64: xilinx: Do not use '_' in DT node namesMichal Simek 2023-07-27arm64: zynqmp: Describe interrupts by using macrosMichal Simek 2023-07-10arm64: zynqmp: Fix dwc3 usb interrupt descriptionMichal Simek 2023-07-10arm64: zynqmp: Setting default i2c clock frequency to 400kHzVaralaxmi Bingi 2023-07-10arm64: zynqmp: Add L2 cache nodesRadhey Shyam Pandey 2023-06-05arm64: zynqmp: Add pmu interrupt-affinityRadhey Shyam Pandey 2023-06-05arm64: zynqmp: Switch to amd.com emailsMichal Simek 2023-05-16arm64: zynqmp: Add phase tags markingMichal Simek 2023-05-16arm64: zynqmp: Sync node name address with reg (mailbox)Michal Simek 2023-05-16arm64: zynqmp: Add resets property to sdhci nodesSai Krishna Potthuri 2023-05-16arm64: zynqmp: Rename ams_ps/pl node namesMichal Simek 2023-05-12Revert "arm64: dts: zynqmp: Add address-cells property to interrupt controllers"Michal Simek 2023-05-12arm64: zynqmp: Add mali-400 gpu node for zynqmpParth Gajjar 2023-01-19arm64: dts: zynqmp: Add xlnx prefix to GEM compatible stringHarini Katakam 2023-01-05arm64: dts: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsiMichal Simek 2023-01-05arm64: dts: zynqmp: Add mode-pin GPIO controller DT nodePiyush Mehta 2023-01-05arm64: zynqmp: Enable hs termination flag for USB dwc3 controllerMichael Grzeschik 2023-01-05arm64: xilinx: Fix opp-table-cpuMichal Simek