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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2019-09-04 14:34:17 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-09-04 17:07:57 -0700 |
| commit | 4444df6e205bc1dc16ba112588815defe3c5a724 (patch) | |
| tree | 0b8ecf5a888ceaf8454cf229fe5ed877a2c87e68 /tools/perf/scripts/python/stackcollapse.py | |
| parent | e468ff06157a3bb1b70ac8ea807429446b8bf4b2 (diff) | |
| download | kernel-4444df6e205bc1dc16ba112588815defe3c5a724.tar.gz | |
drm/i915/tgl: move DP_TP_* to transcoder
Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This adds the new register addresses and changes all
the callers to use the register saved in intel_dp->regs.*. This is
filled out when preparing to enable the port so we take into account if
we should use the transcoder or the port.
v2: reimplement by stashing the registers we want to access under
intel_dp->reg. Now they are initialized when enabling the port.
Ville suggested to store the transcoder to be used exclusively
by TGL+. After implementing I thought just storing the register directly
made it cleaner.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190904213419.27547-5-jose.souza@intel.com
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions