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authorHarsh Jain <harsh@chelsio.com>2018-12-11 16:21:40 +0530
committerHerbert Xu <herbert@gondor.apana.org.au>2018-12-23 11:52:43 +0800
commitfef4912b66d6246d958d97382d20d0dd23bcf0bc (patch)
treec006abbd0dbdf45c4a5780d7ffc4f4c1df968b26 /tools/perf/scripts/python/parallel-perf.py
parentc4f6d44d774eff382b6fc79a9fe1ff376b5ac6d7 (diff)
downloadkernel-fef4912b66d6246d958d97382d20d0dd23bcf0bc.tar.gz
crypto: chelsio - Handle PCI shutdown event
chcr receives "CXGB4_STATE_DETACH" event on PCI Shutdown. Wait for processing of inflight request and Mark the device unavailable. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.3 (git 2.46.0) at 2026-08-17 02:17:16 +0000
17c40537c5babfa7f261360d5a98e434d59e'>arm64: dts: qcom: qcs8300: Partially revert "arm64: dts: qcom: qcs8300: add ↵Krzysztof Kozlowski QCrypto nodes" Partially revert commit a86d84409947 ("arm64: dts: qcom: qcs8300: add QCrypto nodes") by dropping the untested QCE device node. Devicetree bindings test failures were reported on mailing list on 16th of January and after two weeks still no fixes: qcs8300-ride.dtb: crypto@1dfa000: compatible: 'oneOf' conditional failed, one must be fixed: ... 'qcom,qcs8300-qce' is not one of ['qcom,ipq4019-qce', 'qcom,sm8150-qce'] Reported-by: Rob Herring <robh@kernel.org> Closes: https://lore.kernel.org/all/CAL_JsqL0HzzGXnCD+z4GASeXNsBxrdw8-qyfHj8S+C2ucK6EPQ@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250128115333.95021-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-02-25arm64: dts: qcom: qcs8300: Add QUPv3 configurationViken Dadhaniya Add DT support for QUPV3 Serial Engines. Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20250224063338.27306-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-02-21arm64: dts: qcom: qcs8300: Adds SPMI supportTingguo Cheng Add the SPMI bus arbiter(Version:5.2.0) node for QCS8300 SoC which connected with PMICs on QCS8300 boards. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Tingguo Cheng <quic_tingguoc@quicinc.com> Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-1-ee94642279ff@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-01-07arm64: dts: qcom: qcs8300: Add support for usb nodesKrishna Kurapati Add support for USB controllers on QCS8300. The second controller is only High Speed capable. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241114055152.1562116-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-01-07arm64: dts: qcom: qcs8300: Add support for clock controllersImran Shaik Add support for GPU, Video, Camera and Display clock controllers on Qualcomm QCS8300 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20241114-qcs8300-mm-cc-dt-patch-v1-1-7a974508c736@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-01-07arm64: dts: qcom: qcs8300: add the first 2.5G ethernetYijie Yang Add the node for the first ethernet interface on qcs8300 platform. Add the internal SGMII/SerDes PHY node as well. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> Link: https://lore.kernel.org/r/20241206-dts_qcs8300-v5-1-422e4fda292d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-01-07arm64: dts: qcom: qcs8300: Add capacity and DPC propertiesJingyi Wang The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn is used by EAS to take placement decisions. So add it to QCS8300 SoC. Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241206-qcs8300_dpc-v1-1-af2e8e6d3da9@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2025-01-06arm64: dts: qcom: correct gpio-ranges for QCS8300Lijuan Gao Correct the gpio-ranges for the QCS8300 TLMM pin controller to include GPIOs 0-132 and the UFS_RESET pin for primary UFS memory reset. Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform") Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241219-correct_gpio_ranges-v2-6-19af8588dbd0@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-26arm64: dts: qcom: qcs8300: Add LLCC support for QCS8300Jingyi Wang Add Last Level Cache Controller node on the QCS8300 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-3-bb56952cb83b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-26arm64: dts: qcom: qcs8300: Add PMU support for QCS8300Jingyi Wang Add Performance Monitoring Unit(PMU) nodes on the QCS8300 platform. Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241101-qcs8300_pmu-v1-1-3f3d744a3482@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-26arm64: dts: qcom: qcs8300: Add coresight nodesJie Gan Add following coresight components for QCS8300 platform. It includes CTI, dummy sink, dynamic Funnel, Replicator, STM, TPDM, TPDA and TMC ETF. Signed-off-by: Jie Gan <quic_jiegan@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241219024208.3462358-1-quic_jiegan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-25arm64: dts: qcom: qcs8300: enable the inline crypto engineYuvaraj Ranganathan Add an ICE node to qcs8300 SoC description and enable it by adding a phandle to the UFS node. Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> Link: https://lore.kernel.org/r/20241125065801.1751256-3-quic_yrangana@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-25arm64: dts: qcom: qcs8300: add TRNG nodeYuvaraj Ranganathan The qcs8300 SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241125064317.1748451-3-quic_yrangana@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-25arm64: dts: qcom: qcs8300: Add ADSP and CDSP0 fastrpc nodesLing Xu Add ADSP and CDSP0 fastrpc nodes for QCS8300 platform. Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241119120635.687936-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-25arm64: dts: qcom: qcs8300: add QCrypto nodesYuvaraj Ranganathan Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241223110936.3428125-1-quic_yrangana@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> 2024-12-19arm64: dts: qcom: qcs8300: Add watchdog nodeXin Liu Add the watchdog node for QCS8300 SoC. Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> 2024-12-03arm64: dts: qcom: add QCS8300 platformJingyi Wang Add initial DTSI for QCS8300 SoC. Features added in this revision: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect - QuP with uart - SMMU - QFPROM - Rpmhpd power controller - UFS - Inter-Processor Communication Controller - SRAM - Remoteprocs including ADSP,CDSP and GPDSP - BWMONs Written with help from Zhenhua Huang(added the smmu node), Xin Liu(added ufs, adsp and gpdsp nodes), Tingguo Cheng(added the rpmhpd node), Kyle Deng(added the aoss_qmp node), Raviteja Laggyshetty(added interconnect nodes) and Cong Zhang(added the INTID of EL2 non-secure physical timer). Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> Link: https://lore.kernel.org/r/20241203-qcs8300_initial_dtsi-v4-3-d7c953484024@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>