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| author | Paul Selles <paul.selles@microchip.com> | 2018-12-06 21:30:50 +0800 |
|---|---|---|
| committer | Jon Mason <jdmason@kudzu.us> | 2019-02-11 07:36:13 -0500 |
| commit | cce8e04cf79e47809455215744685e8eb56f94bb (patch) | |
| tree | fa8a1d7b22ba7238ff38efe19a0b7684a46a83af /tools/perf/scripts/python/parallel-perf.py | |
| parent | bfeffd155283772bbe78c6a05dec7c0128ee500c (diff) | |
| download | kernel-cce8e04cf79e47809455215744685e8eb56f94bb.tar.gz | |
ntb_hw_switchtec: debug print 64bit aligned crosslink BAR Numbers
Switchtec NTB crosslink BARs are 64bit addressed but they are printed as
32bit addressed BARs. Fix debug log to increment the BAR numbers by 2 to
reflect the 64bit address alignment.
Fixes: 017525018202 ("ntb_hw_switchtec: Add initialization code for crosslink")
Signed-off-by: Paul Selles <paul.selles@microchip.com>
Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions