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authorClaudiu Beznea <claudiu.beznea@microchip.com>2019-12-18 14:28:24 +0200
committerSam Ravnborg <sam@ravnborg.org>2020-01-06 19:52:53 +0100
commit07acf4bafe81dd37eff3fbcfbbdbc48084bc202b (patch)
treeb2031ddd15d3bccf410cbef0e9421268660e8a56 /tools/perf/scripts/python/parallel-perf.py
parentbf046007641a7ef76d4ed976ac67bf24d05ac51a (diff)
downloadkernel-07acf4bafe81dd37eff3fbcfbbdbc48084bc202b.tar.gz
drm: atmel-hlcdc: use double rate for pixel clock only if supported
Doubled system clock should be used as pixel cock source only if this is supported. This is emphasized by the value of atmel_hlcdc_crtc::dc::desc::fixed_clksrc. Fixes: a6eca2abdd42 ("drm: atmel-hlcdc: add config option for clock selection") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: <stable@vger.kernel.org> # v5.3+ Link: https://patchwork.freedesktop.org/patch/msgid/1576672109-22707-2-git-send-email-claudiu.beznea@microchip.com
Diffstat (limited to 'tools/perf/scripts/python/parallel-perf.py')
0 files changed, 0 insertions, 0 deletions
tarfive: add PCIe dts configuration for JH7110Minda Chen Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has one exposed PCIe port, so only the Mars and VisionFive 2 get two enabled. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> [conor: squash in star64's single exposed port] Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 2024-04-30riscv: dts: starfive: add Milkv Mars board device treeJisheng Zhang The Milkv Mars is a development board based on the Starfive JH7110 SoC. The board features: - JH7110 SoC - 1/2/4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 3x USB 3.0 host port - 1x USB 2.0 host port - 1x M.2 E-Key - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 1x 1Gbps Ethernet port - 1x HDMI port - 1x 2-lane DSI and 1x 4-lane DSI - 1x 2-lane CSI Add the devicetree file describing the currently supported features, namely PMIC, UART, I2C, GPIO, SD card, QSPI Flash, eMMC and Ethernet. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>