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authorAl Viro <viro@zeniv.linux.org.uk>2025-03-08 19:54:09 -0500
committerAl Viro <viro@zeniv.linux.org.uk>2025-07-02 22:36:51 -0400
commiteacb58fdcaefac63d32c3c095152e97dc9425ea8 (patch)
tree0b91dee0057474ebda76c9dc5c1f39809378f9f5 /tools/perf/scripts/python/netdev-times.py
parent8c0e092e3875fe834ca37a2953c91cb42cc0ceeb (diff)
downloadkernel-eacb58fdcaefac63d32c3c095152e97dc9425ea8.tar.gz
binfmt_misc: switch to locked_recursive_removal()
... fixing a mount leak, strictly speaking. Reviewed-by: Christian Brauner <brauner@kernel.org> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/netdev-times.py')
0 files changed, 0 insertions, 0 deletions
.net Patchwork: https://patchwork.linux-mips.org/patch/3316/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2012-07-23MIPS: BCM63xx: Define SPI register sizes.Florian Fainelli There are two distinct sizes for the SPI register depending on the SoC generation (6338 & 6348 vs 6358 & 6368). Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Patchwork: https://patchwork.linux-mips.org/patch/3314/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2012-07-23MIPS: BCM63xx: Define BCM6358 SPI base addressFlorian Fainelli Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Patchwork: https://patchwork.linux-mips.org/patch/3315/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2012-07-23MIPS: BCM63xx: Add IRQ_SPI and CPU specific SPI IRQ valuesFlorian Fainelli Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Patchwork: https://patchwork.linux-mips.org/patch/3320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2011-12-07MIPS: BCM63xx: Remove BCM6345 hacks to read base boot addressFlorian Fainelli Though BCM6345 does not technically have the same MPI register layout than the other SoCs, reading the chip-select registers is done the same way, and particularly for chip-select 0, which is the boot flash. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2011-12-07MIPS: BCM63XX: Add support for bcm6368 CPU.Maxime Bizon Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2011-12-07MIPS: BCM63XX: Add more register sets & missing register definitions.Maxime Bizon Needed for upcoming 6368 CPU support. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2893/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2011-12-07MIPS: BCM63XX: Cleanup cpu registers.Maxime Bizon Use preprocessor when possible to avoid duplicated and error-prone code. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2897/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2010-04-12MIPS: BCM63xx: Add support for second uart.Maxime Bizon The BCm63xx SOC has two uarts. Some boards use the second one for bluetooth. This patch changes platform device registration code to handle this. Changes to the UART driver were already merged in 6a2c7eabfd09ca7986bf96b8958a87ca041a19d8. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> To: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Patchwork: http://patchwork.linux-mips.org/patch/900/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>