summaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/flamegraph.py
diff options
context:
space:
mode:
authorTakashi Iwai <tiwai@suse.de>2013-01-10 17:41:54 +0100
committerTakashi Iwai <tiwai@suse.de>2013-01-10 17:41:54 +0100
commitc18ab0bac4c377b22e03f9cd4efafa1316b76552 (patch)
tree57049641755e7e01d6da9a902ac662a28b688b0b /tools/perf/scripts/python/flamegraph.py
parent065380f0880dd651eb405430745926dc4747b759 (diff)
parent49a170bcf28af5ef372cdbed7750ba8d4162bb0e (diff)
downloadkernel-c18ab0bac4c377b22e03f9cd4efafa1316b76552.tar.gz
Merge tag 'asoc-fix-3.8-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Fixes for v3.8 Nothing terribly exciting here except for the DOUBLE_RANGE fix which just hadn't worked before, nobody noticed due to lack of use.
Diffstat (limited to 'tools/perf/scripts/python/flamegraph.py')
0 files changed, 0 insertions, 0 deletions
href='/distro/kernel/commit/drivers/gpu/drm/i915/display/intel_lt_phy.c?id=ad7108f966fe38e19a7423a1dafca835b78185b7'>drm/i915/ltphy: Modify the step that need to be skippedSuraj Kandpal 2025-11-01drm/i915/ltphy: Define LT PHY PLL state verify functionSuraj Kandpal 2025-11-01drm/i915/ltphy: Define function to readout LT Phy PLL stateSuraj Kandpal 2025-11-01drm/i915/ltphy: Define the LT Phy state compare functionSuraj Kandpal 2025-11-01drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program LT Phy Voltage SwingSuraj Kandpal 2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal 2025-11-01drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL stepsSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal 2025-11-01drm/i915/ltphy: Add function to calculate LT PHY port clockSuraj Kandpal 2025-11-01drm/i915/ltphy: Enable SSC during port clock programmingSuraj Kandpal 2025-11-01drm/i915/ltphy: Update the ltpll config table value for eDPSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal 2025-11-01drm/i915/ltphy: Add LT Phy Programming recipe tablesSuraj Kandpal 2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal 2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT PhySuraj Kandpal 2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal