diff options
| author | Chris Park <Chris.Park@amd.com> | 2022-03-15 12:21:43 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-03-31 23:05:53 -0400 |
| commit | 83bb503275bdf651c67f02e0d25f2d0db2ca865b (patch) | |
| tree | 08b0cb9848ffdc76787d740ff777e40f2da6872a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | e9ebc23b3fb2949e18c6df98a6e6fd94429e498e (diff) | |
| download | kernel-83bb503275bdf651c67f02e0d25f2d0db2ca865b.tar.gz | |
drm/amd/display: Correct Slice reset calculation
[Why]
Once DSC slice cannot fit pixel clock, we incorrectly
reset min slices to 0 and allow max slice to operate,
even when max slice itself cannot fit the pixel clock
properly.
[How]
Change the sequence such that we correctly determine
DSC is not possible when both min slices and max
slices cannot fit pixel clock per slice.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions