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authorSakari Ailus <sakari.ailus@linux.intel.com>2018-04-12 06:12:17 -0400
committerMauro Carvalho Chehab <mchehab@s-opensource.com>2018-04-23 13:56:46 -0400
commit31b9cb6ecd0128a165fe2b437ef63a6fa744de7b (patch)
tree1c5a2dea4114b84bef9cb46b9c9779d823fd5b89 /tools/perf/scripts/python/export-to-postgresql.py
parent46799197c073ef54d695acf87dd592cab7f6b251 (diff)
downloadkernel-31b9cb6ecd0128a165fe2b437ef63a6fa744de7b.tar.gz
media: ov7740: Fix number of controls hint
The driver has 12 controls, not 2. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions
d>Gustavo A. R. Silva Currently clkoutdiv is being operated on by a logical && operator rather than a bitwise & operator. This looks incorrect as these should be bit flag operations. Addresses-Coverity-ID: 1463959 ("Logical vs. bitwise operator") Fixes: cee8113a295a ("soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2018-01-08soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driverDhaval Shah Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>