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authorClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>2023-10-06 13:39:59 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2023-10-10 09:29:48 +0200
commitde60a3ebe410670ffdbbc95faa25a820da44ab11 (patch)
treeda8d3bd91aaf1a7c5f96bc04052bb7f86ea48eaf /tools/perf/scripts/python/bin
parenta96aed0636d49f39e4c9eb85ef7c8630e12e3421 (diff)
downloadkernel-de60a3ebe410670ffdbbc95faa25a820da44ab11.tar.gz
clk: renesas: Add minimal boot support for RZ/G3S SoC
Add minimal clock and reset support for the RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, and SD0 module clocks and resets. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231006103959.197485-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions
--- potentially unexpected fatal signal 4. Path: /munmap01 CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8 task: 9f1a8000 ti: 9f154000 task.ti: 9f154000 [ECR ]: 0x00020100 => Illegal Insn [EFA ]: 0x0001354c [BLINK ]: 0x200515d4 [ERET ]: 0x1354c @off 0x1354c in [/munmap01] VMA: 0x00010000 to 0x00018000 [STAT32]: 0x800802c0 ... --------------------->8-------------------------------------- The issue was 1. munmap01 accessed unmapped memory (on purpose) with signal handler installed for SIGSEGV 2. The faulting instruction happened to be in Delay Slot 00011864 <main>: 11908: bl.d 13284 <tst_resm> 1190c: stb r16,[r2] 3. kernel sets up the reg file for signal handler and correctly clears the DE bit in pt_regs->status32 placeholder 4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2, and it over-writes the above with orig/stale value of status32 5. After RTIE, userspace signal handler executes a non branch instruction with DE bit set, triggering Illegal Instruction Exception. Reported-by: Anton Kolesov <akolesov@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> 2015-06-22ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com> 2015-06-19ARC: entry.S: split into ARCompact ISA specific, common bitsVineet Gupta Signed-off-by: Vineet Gupta <vgupta@synopsys.com> 2015-06-19ARC: entry.S: FAKE_RET_FROM_EXCPN can always use r9Vineet Gupta Signed-off-by: Vineet Gupta <vgupta@synopsys.com> 2015-06-19ARC: entry.S: canonical'ize EXCEPTION_{PROLOGUE,EPILOGUE}Vineet Gupta -EXCEPTION_EPILOGUE introduced -EXCEPTION_PROLOGUE now also includes reg file saving Signed-off-by: Vineet Gupta <vgupta@synopsys.com> 2015-06-19ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}Vineet Gupta -common'ize macros for level 1 and level 2 interrupts Signed-off-by: Vineet Gupta <vgupta@synopsys.com> 2015-06-19ARC: entry.S: common'ize scrtach reg freeup in intr + exceptionsVineet Gupta Signed-off-by: Vineet Gupta <vgupta@synopsys.com>