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authorZhang Qilong <zhangqilong3@huawei.com>2020-11-13 21:18:56 +0800
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-11-17 12:53:57 +0100
commitac3b57adf87ad9bac7e33ca26bbbb13fae1ed62b (patch)
treebcc067bf053fd37cd99a3806b492c4b4c04f6406 /tools/perf/scripts/python/bin
parent61a2f1aecf6052f7bcf900829ca2b9d74437ec07 (diff)
downloadkernel-ac3b57adf87ad9bac7e33ca26bbbb13fae1ed62b.tar.gz
MIPS: Alchemy: Fix memleak in alchemy_clk_setup_cpu
If the clk_register fails, we should free h before function returns to prevent memleak. Fixes: 474402291a0ad ("MIPS: Alchemy: clock framework integration of onchip clocks") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions
0800'>2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky 2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky 2021-11-15ACPI: NUMA: Add a node and memblk for each CFMWS not in SRATAlison Schofield 2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams 2021-11-15cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpersDan Williams 2021-10-08cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBSAlison Schofield 2021-09-21cxl/core: Split decoder setup into alloc + addDan Williams 2021-09-21cxl/bus: Populate the target list at decoder createDan Williams 2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams 2021-09-07cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge portsAlison Schofield 2021-06-17cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield 2021-06-17cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield 2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams 2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams 2021-06-09cxl/acpi: Enumerate host bridge root portsDan Williams 2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams 2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams