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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2022-07-24 17:04:20 +0300
committerBjorn Andersson <andersson@kernel.org>2022-10-17 13:55:26 -0500
commit0d440d811e6e2f37093e54db55bc27fe66678170 (patch)
treeff682969f58e4b3d22cc1891c8beea35e15fed1e /tools/perf/scripts/python/bin
parentf1646de452ae8a9b858cefc2087c0ab93ac5c0ad (diff)
downloadkernel-0d440d811e6e2f37093e54db55bc27fe66678170.tar.gz
arm64: dts: qcom: msm8996: fix GPU OPP table
Fix Adreno OPP table according to the msm-3.18. Enable 624 MHz for the speed bin 3 and 560 MHz for bins 2 and 3. Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-7-dmitry.baryshkov@linaro.org
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59:00 +0300'>2016-04-29drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.cAnder Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate pre encoder enabling phy codeAnder Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate VLV phy pre pll enabling codeAnder Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate VLV signal level codeAnder Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate CHV encoders' post pll disable codeAnder Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate CHV pre-encoder enabling phy logicAnder Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate CHV phy-releated pre pll enabling codeAnder Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate chv_data_lane_soft_reset()Ander Conselvan de Oliveira 2016-04-29drm/i915: Unduplicate CHV signal level codeAnder Conselvan de Oliveira