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| author | José Roberto de Souza <jose.souza@intel.com> | 2019-08-23 01:20:47 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2019-08-27 08:47:31 -0700 |
| commit | 99389390fef50c880d2ca0b6667c12423b3d5260 (patch) | |
| tree | c74262a05ec8d6f2318d2cf80b834102484d73a3 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 9c722e17c1b91d7dc5ec77cb4fcaaa6b30653fe3 (diff) | |
| download | kernel-99389390fef50c880d2ca0b6667c12423b3d5260.tar.gz | |
drm/i915/tgl: Implement TGL DisplayPort training sequence
On TGL some registers moved from DDI to transcoder and the
DisplayPort training sequence has a separate BSpec page.
I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
it was becoming really hard to follow, so a new and cleaner function
for TGL was added with comments of all steps. It's similar to ICL,
but different enough to deserve a new function.
The rest of DisplayPort enable and the whole disable sequences
remained the same.
v2: FEC and DSC should be enabled on sink side before start link
training(Maarten reported and Manasi confirmed the DSC part)
v3: Add call to enable FEC on step 7.l(Manasi)
BSpec: 49190
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-16-lucas.demarchi@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions