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| author | Matt Roper <matthew.d.roper@intel.com> | 2019-09-10 09:05:20 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2019-09-10 20:35:36 -0700 |
| commit | 71dc367e2bc37e1c235029003fbbc56a07fb6d58 (patch) | |
| tree | 97eb141cf91a9f6bf0b2c1fe3691c39a202b3fb2 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | ab37c4d712c8b35c0c1e3237e04fe49f717055a4 (diff) | |
| download | kernel-71dc367e2bc37e1c235029003fbbc56a07fb6d58.tar.gz | |
drm/i915: Consolidate bxt/cnl/icl cdclk readout
Aside from a few minor register changes and some different clock values,
cdclk design hasn't changed much since gen9lp. Let's consolidate the
handlers for bxt, cnl, and icl to keep the codeflow consistent.
Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
"update" makes me think we should be writing to hardware rather than
reading from it.
v2:
- Fix icl_calc_voltage_level() limits. (Ville)
- Use CNL_CDCLK_PLL_RATIO_MASK rather than BXT_DE_PLL_RATIO_MASK on
gen10+ to avoid confusion. (Ville)
v3:
- Also fix ehl_calc_voltage_level() limits. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190910160520.6587-1-matthew.d.roper@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions