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authorFiroz Khan <firoz.khan@linaro.org>2018-11-13 15:01:49 +0530
committerMatt Turner <mattst88@gmail.com>2018-12-21 11:57:56 -0500
commit150fbd536f9eb3044c2b048dc13ee648a78afb93 (patch)
tree5d0d196fdb21617367190fff392681b98505a859 /tools/perf/scripts/python/bin/stackcollapse-report
parent9097a058d49e049925d8da72db07fffcee24efa0 (diff)
downloadkernel-150fbd536f9eb3044c2b048dc13ee648a78afb93.tar.gz
alpha: move __IGNORE* entries to non uapi header
All the __IGNORE* entries are resides in the uapi header file move to non uapi header asm/unistd.h as it is not used by any user space applications. It is correct to keep __IGNORE* entry in non uapi header asm/unistd.h while uapi/asm/unistd.h must hold information only useful for user space applications. One of the patch in this patch series will generate uapi header file. The information which directly used by the user space application must be present in uapi file. Signed-off-by: Firoz Khan <firoz.khan@linaro.org> Signed-off-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions
b09af49452cf000ee7924da5bc0a8'>drm/i915/ltphy: Define the LT Phy state compare functionSuraj Kandpal 2025-11-01drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program LT Phy Voltage SwingSuraj Kandpal 2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal 2025-11-01drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL stepsSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal 2025-11-01drm/i915/ltphy: Add function to calculate LT PHY port clockSuraj Kandpal 2025-11-01drm/i915/ltphy: Enable SSC during port clock programmingSuraj Kandpal 2025-11-01drm/i915/ltphy: Update the ltpll config table value for eDPSuraj Kandpal 2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal 2025-11-01drm/i915/ltphy: Add LT Phy Programming recipe tablesSuraj Kandpal 2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal 2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal 2025-11-01drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT PhySuraj Kandpal 2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal