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| author | Zhou Wang <wangzhou1@hisilicon.com> | 2019-08-02 15:57:51 +0800 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2019-08-09 15:11:53 +1000 |
| commit | dfed0098ab91f647b5720ab6f1e03b5b55139408 (patch) | |
| tree | 7e195fc299279dd885b41527ee4bb003951a09a6 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 263c9959c9376ec0217d6adc61222a53469eed3c (diff) | |
| download | kernel-dfed0098ab91f647b5720ab6f1e03b5b55139408.tar.gz | |
crypto: hisilicon - add hardware SGL support
HiSilicon accelerators in Hip08 use same hardware scatterlist for data format.
We support it in this module.
Specific accelerator drivers can use hisi_acc_create_sgl_pool to allocate
hardware SGLs ahead. Then use hisi_acc_sg_buf_map_to_hw_sgl to get one
hardware SGL and pass related information to hardware SGL.
The DMA address of mapped hardware SGL can be passed to SGL src/dst field
in QM SQE.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions