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| author | Yunfei Dong <yunfei.dong@mediatek.com> | 2023-03-03 01:38:41 +0000 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@kernel.org> | 2023-04-10 14:01:39 +0100 |
| commit | cdc1068ab63abe13d696c9985f86ca8a40c2798f (patch) | |
| tree | 2620c7835e3f6f7a8748e39db6eda31bcaf15998 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 355e9472ccb05f3744b757e5174d476d2b7d5cbc (diff) | |
| download | kernel-cdc1068ab63abe13d696c9985f86ca8a40c2798f.tar.gz | |
media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2
Need to add racing control register base in device node for mt8195 support
inner racing mode. Changing the max reg value from 1 to 2.
Adding the description for VDEC_SYS and VDEC_MISC.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions