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| author | Neil Armstrong <neil.armstrong@linaro.org> | 2025-02-11 13:56:38 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-02-21 15:50:32 -0600 |
| commit | c9658c3963b8a5ebe488acfa2609fc641a126b60 (patch) | |
| tree | dba55b376ab4011f915288b4d07127e4b1a3f2f1 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 62a770da5327910233ff0b0e1989e14feb3d766e (diff) | |
| download | kernel-c9658c3963b8a5ebe488acfa2609fc641a126b60.tar.gz | |
arm64: dts: qcom: sm8650: add cpu interconnect nodes
Add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-2-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions