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authorViresh Kumar <viresh.kumar@linaro.org>2021-01-19 11:58:58 +0530
committerViresh Kumar <viresh.kumar@linaro.org>2021-02-02 10:27:39 +0530
commit38bb34393804b79eff647bdf96762db5efce392c (patch)
tree802bbdfbe035ad2af4337874435acf0024708b10 /tools/perf/scripts/python/bin/stackcollapse-record
parentb6ecd5d4f6941628d0140735d3f05eb61907141e (diff)
downloadkernel-38bb34393804b79eff647bdf96762db5efce392c.tar.gz
opp: Prepare for ->set_opp() helper to work without regulators
Until now the ->set_opp() helper (i.e. special implementation for setting the OPPs for platforms) was implemented only to take care of multiple regulators case, but going forward we would need that for other use cases as well. This patch prepares for that by allocating the regulator specific part from dev_pm_opp_set_regulators() and the opp helper part from dev_pm_opp_register_set_opp_helper(). Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Tested-by: Dmitry Osipenko <digetx@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions
ers/gpu/drm/amd/display/dc/dcn301?h=master&id=31484207feb23e6cdb12827560442ab294855923'>drm/amd/display: move FPU associated DCN301 code to DML folderQingqing Zhuo 2021-09-23drm/amd/display: Use adjusted DCN301 watermarksNikola Cornij 2021-09-14drm/amd/display: Fix multiple memory leaks reported by coverityAnson Jacob 2021-08-18drm/amd/display: Use DCN30 watermark calc for DCN301Zhan Liu 2021-07-21drm/amd/display: log additional register state for debugJosip Pavic 2021-06-08drm/amd/display: Add interface for ADD & DROP PIXEL RegistersWesley Chalmers 2021-06-08drm/amd/display: Add Interface to set FIFO ERRDET SW OverrideWesley Chalmers 2021-06-08drm/amd/display: Refactor visual confirmWyatt Wood 2021-05-27Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"Qingqing Zhuo 2021-05-19drm/amd/display: Fix typo of format termination newlineJoe Perches 2021-05-19drm/amd/display: Refactor and add visual confirm for HW Flip QueueWyatt Wood 2021-05-19drm/amd/display: Use the correct max downscaling value for DCN3.x familyNikola Cornij 2021-04-15drm/amd/display: Connect clock optimization function to dcn301Mikita Lipski 2021-04-09drm/amd/display: Add function and debugfs to dump DCC_EN bitVictor Lu 2021-04-09drm/amd/display: Add dc_debug flag to disable min fclkHarry Wentland 2021-04-09drm/amd/display: revert max lb lines changeDmytro Laktyushkin 2021-03-26Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/ag...Daniel Vetter 2021-03-23drm/amd/display: fix dcn3+ bw validation soc param update sequenceDmytro Laktyushkin 2021-03-23drm/amd/display: Separate caps for maximum RGB and YUV plane countsAtufa Khan