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| author | Leonard Crestez <leonard.crestez@nxp.com> | 2018-07-20 15:47:43 +0300 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2018-07-23 13:00:28 +0200 |
| commit | 26fce0557fa639fb7bbc33e31a57cff7df25c3a0 (patch) | |
| tree | 349e7e2253fe0cd9768f2d829c2cc2063d7d6cc2 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | ce397d215ccd07b8ae3f71db689aedb85d56ab40 (diff) | |
| download | kernel-26fce0557fa639fb7bbc33e31a57cff7df25c3a0.tar.gz | |
reset: imx7: Fix always writing bits as 0
Right now the only user of reset-imx7 is pci-imx6 and the
reset_control_assert and deassert calls on pciephy_reset don't toggle
the PCIEPHY_BTN and PCIEPHY_G_RST bits as expected. Fix this by writing
1 or 0 respectively.
The reference manual is not very clear regarding SRC_PCIEPHY_RCR but for
other registers like MIPIPHY and HSICPHY the bits are explicitly
documented as "1 means assert, 0 means deassert".
The values are still reversed for IMX7_RESET_PCIE_CTRL_APPS_EN.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions