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| author | Uma Shankar <uma.shankar@intel.com> | 2025-12-03 14:22:05 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2025-12-04 19:43:47 +0200 |
| commit | 05df71544c44a1767be021285648c090123a92ff (patch) | |
| tree | cfdacc1d138e6d6d9b2b716d500318eb4fccfd19 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | ed0ebbc89f847eebce790a6a308c8c3c1251655a (diff) | |
| download | kernel-05df71544c44a1767be021285648c090123a92ff.tar.gz | |
drm/i915: Add register definitions for Plane Post CSC
Add macros to define Plane Post CSC registers
v2:
- Add Plane Post CSC Gamma Multi Segment Enable bit
- Add BSpec entries (Suraj)
v3:
- Fix checkpatch issues (Suraj)
BSpec: 50403, 50404, 50405, 50406, 50409, 50410,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20251203085211.3663374-10-uma.shankar@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions