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authorSasha Levin <sashal@kernel.org>2026-03-04 07:36:34 -0500
committerSasha Levin <sashal@kernel.org>2026-03-04 07:37:37 -0500
commit91d48252ad4b17577cf8cc8d3e1353402e4da8f1 (patch)
treeed0b109ed1f2e761db95b740571776daafae1dff /include/linux/kthread.h
parent50d01dcbde56c666ef3ecd7401379fdb76fdd220 (diff)
downloadkernel-linux-5.15.y.tar.gz
Linux 5.15.202linux-5.15.y
Signed-off-by: Sasha Levin <sashal@kernel.org> Tested-by: Hardik Garg <hargar@linux.microsoft.com> Tested-by: Vijayendra Suman <vijayendra.suman@oracle.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/kthread.h')
0 files changed, 0 insertions, 0 deletions
d>Conor Dooley 2022-12-29RISC-V: fix auipc-jalr addresses in patched alternativesHeiko Stuebner 2022-12-09RISC-V: Ensure Zicbom has a valid block sizeAndrew Jones 2022-12-09RISC-V: Introduce riscv_isa_extension_checkAndrew Jones 2022-12-09RISC-V: Improve use of isa2hwcap[]Andrew Jones 2022-10-14Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds 2022-10-13Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt 2022-10-13riscv: use BIT() marco for cpufeature probingHeiko Stuebner 2022-10-13riscv: drop some idefs from CMO initializationHeiko Stuebner 2022-10-13riscv: cleanup svpbmt cpufeature probingHeiko Stuebner 2022-10-02RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale 2022-08-16riscv: Ensure isa-ext static keys are writableAndrew Jones 2022-08-11RISC-V: Add Sstc extension supportPalmer Dabbelt 2022-08-11RISC-V: Enable sstc extension parsing from DTAtish Patra 2022-08-11arch/riscv: add Zihintpause supportDao Lu 2022-08-10riscv: implement Zicbom-based CMO instructions + the t-head variantPalmer Dabbelt 2022-07-28riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner 2022-07-19RISC-V: Support for 64bit hartid on RV64 platformsPalmer Dabbelt 2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L 2022-06-16RISC-V: Some Svpbmt fixes and cleanupsPalmer Dabbelt 2022-06-16riscv: remove usage of function-pointers from cpufeatures and t-head errataHeiko Stuebner 2022-06-16riscv: drop cpufeature_apply_feature tracking variableHeiko Stuebner 2022-06-16riscv: switch has_fpu() to the unified static key mechanismJisheng Zhang 2022-06-16riscv: introduce unified static key mechanism for ISA extensionsJisheng Zhang 2022-06-04Merge tag 'bitmap-for-5.19-rc1' of https://github.com/norov/linuxLinus Torvalds 2022-06-03risc-v: replace bitmap_weight with bitmap_empty in riscv_fill_hwcap()Yury Norov 2022-05-11riscv: add memory-type errata for T-HeadHeiko Stuebner 2022-05-11riscv: add RISC-V Svpbmt extension supportHeiko Stuebner 2022-03-21RISC-V: Add sscofpmf extension supportAtish Patra 2022-03-17RISC-V: Do no continue isa string parsing without correct XLENAtish Patra 2022-03-17RISC-V: Implement multi-letter ISA extension probing frameworkAtish Patra 2022-03-17RISC-V: Extract multi-letter extension names from "riscv, isa"Tsukasa OI 2022-03-17RISC-V: Minimal parser for "riscv, isa" stringsTsukasa OI 2022-03-17RISC-V: Correctly print supported extensionsTsukasa OI 2021-05-29riscv: Add __init section marker to some functions againJisheng Zhang 2021-05-25riscv: Turn has_fpu into a static key if FPU=yJisheng Zhang 2020-05-04RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel