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authorLinus Torvalds <torvalds@linux-foundation.org>2025-12-04 11:24:24 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2025-12-04 11:24:24 -0800
commitfa5ef105618ae9b5aaa51b3f09e41d88d4514207 (patch)
tree30780efabf844cc55a8d27082e6a7810d311d68b /drivers/spi/Kconfig
parent0a9431fa74ac9b744bff5b65082ff96fd3d80297 (diff)
parentcb5c2eb459f4c98d584eaf3d3ea7c3612385d081 (diff)
Merge tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "This release is almost entirely new drivers, with a couple of small changes in generic code. The biggest individual update is a rename of the existing Microchip driver and the addition of a new driver for the silicon SPI controller in their PolarFire SoCs. The overlap between the soft IP supported by the current driver and this new one is regrettably all in the IP and not in the register interface offered to software. - Add a time offset parameter for offloads, allowing them to be defined in relation to each other. This is useful for IIO type applcations where you trigger an operation then read the result after a delay. - Add a tracepoint for flash exec_ops, bringing the flash support more in line with the debuggability of vanilla SPI. - Support for Airoha EN7523, Arduino MCUs, Aspeed AST2700, Microchip PolarFire SPI controllers, NXP i.MX51 ECSPI target mode, Qualcomm IPQ5414 and IPQ5332, Renesas RZ/T2H, RZ/V2N and RZ/2NH and SpacemiT K1 QuadSPI. There's also a small set of ASoC cleanups that I mistakenly applied to the SPI tree and then put more stuff on top of before it was brought to my attention, sorry about that" * tag 'spi-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (80 commits) spi: microchip-core: Refactor FIFO read and write handlers spi: ch341: fix out-of-bounds memory access in ch341_transfer_one spi: microchip-core: Remove unneeded PM related macro spi: microchip-core: Use SPI_MODE_X_MASK spi: microchip-core: Utilise temporary variable for struct device spi: microchip-core: Replace dead code (-ENOMEM error message) spi: microchip-core: use min() instead of min_t() spi: dt-bindings: airoha: add compatible for EN7523 spi: airoha-snfi: en7523: workaround flash damaging if UART_TXD was short to GND spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support spi: microchip: Enable compile-testing for FPGA SPI controllers spi: Fix potential uninitialized variable in probe() spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H spi: dt-bindings: renesas,rzv2h-rspi: document RZ/T2H and RZ/N2H spi: rzv2h-rspi: add support for loopback mode spi: rzv2h-rspi: add support for variable transfer clock spi: rzv2h-rspi: add support for using PCLK for transfer clock spi: rzv2h-rspi: make transfer clock rate finding chip-specific spi: rzv2h-rspi: avoid recomputing transfer frequency ...
Diffstat (limited to 'drivers/spi/Kconfig')
-rw-r--r--drivers/spi/Kconfig31
1 files changed, 21 insertions, 10 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 55675750182e..5520403896fc 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -435,7 +435,8 @@ config SPI_FSL_LPSPI
config SPI_FSL_QUADSPI
tristate "Freescale QSPI controller"
- depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || \
+ ARCH_SPACEMIT || COMPILE_TEST
depends on HAS_IOMEM
help
This enables support for the Quad SPI controller in master mode.
@@ -706,15 +707,6 @@ config SPI_MESON_SPIFC
This enables master mode support for the SPIFC (SPI flash
controller) available in Amlogic Meson SoCs.
-config SPI_MICROCHIP_CORE
- tristate "Microchip FPGA SPI controllers"
- depends on SPI_MASTER
- help
- This enables the SPI driver for Microchip FPGA SPI controllers.
- Say Y or M here if you want to use the "hard" controllers on
- PolarFire SoC.
- If built as a module, it will be called spi-microchip-core.
-
config SPI_MICROCHIP_CORE_QSPI
tristate "Microchip FPGA QSPI controllers"
depends on SPI_MASTER
@@ -724,6 +716,15 @@ config SPI_MICROCHIP_CORE_QSPI
PolarFire SoC.
If built as a module, it will be called spi-microchip-core-qspi.
+config SPI_MICROCHIP_CORE_SPI
+ tristate "Microchip FPGA CoreSPI controller"
+ depends on SPI_MASTER
+ help
+ This enables the SPI driver for Microchip FPGA CoreSPI controller.
+ Say Y or M here if you want to use the "soft" controllers on
+ PolarFire SoC.
+ If built as a module, it will be called spi-microchip-core-spi.
+
config SPI_MT65XX
tristate "MediaTek SPI controller"
depends on ARCH_MEDIATEK || COMPILE_TEST
@@ -871,6 +872,16 @@ config SPI_PL022
controller. If you have an embedded system with an AMBA(R)
bus and a PL022 controller, say Y or M here.
+config SPI_POLARFIRE_SOC
+ tristate "Microchip FPGA SPI controllers"
+ depends on SPI_MASTER
+ depends on ARCH_MICROCHIP || COMPILE_TEST
+ help
+ This enables the SPI driver for Microchip FPGA SPI controllers.
+ Say Y or M here if you want to use the "hard" controllers on
+ PolarFire SoC.
+ If built as a module, it will be called spi-mpfs.
+
config SPI_PPC4xx
tristate "PPC4xx SPI Controller"
depends on PPC32 && 4xx