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author0x221E <0x221E@0xinfinity.dev>2026-04-12 23:14:34 +0200
committer0x221E <0x221E@0xinfinity.dev>2026-05-03 00:28:51 +0200
commitead848e141dbd0e71c94e519dc413a02e158d064 (patch)
tree9e0bcd0c11fc30ac8714a088477f40f5c586d8dd /drivers/reset/amlogic/Kconfig
parentfb00be0c81933d947e120a00dff0c3b26e08b466 (diff)
downloadkernel-0x221E-v0.0-v7.0.tar.gz
potential firmware bug on intel hda sound.HEADv0.0.1-v7.00x221E-v0.0-v7.0
Firmware disables MSI causing legacy irqs to be used for intel audio chipsets. However, on my device it causes powertop to display Alderlake as being used 100% and "Disabling MSI" to be printed.
Diffstat (limited to 'drivers/reset/amlogic/Kconfig')
0 files changed, 0 insertions, 0 deletions
generated by cgit v1.2.3 (git 2.46.0) at 2026-07-22 01:19:57 +0000
ajkowski Make the burst length configurable by the drivers. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net> 2021-09-15MIPS: lantiq: dma: fix burst length for DEUAleksander Jan Bajkowski The current definition of 2W burst length is invalid. This patch fixes it. Current downstream DEU driver doesn't use DMA. An incorrect burst length value doesn't cause any errors. This patch also adds other burst length values. Fixes: dfec1a827d2b ("MIPS: Lantiq: Add DMA support") Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net> 2021-09-15MIPS: lantiq: dma: reset correct number of channelAleksander Jan Bajkowski Different SoCs have a different number of channels, e.g .: * amazon-se has 10 channels, * danube+ar9 have 20 channels, * vr9 has 28 channels, * ar10 has 24 channels. We can read the ID register and, depending on the reported number of channels, reset the appropriate number of channels. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net> 2021-09-15MIPS: lantiq: dma: add small delay after resetAleksander Jan Bajkowski Reading the DMA registers immediately after the reset causes Data Bus Error. Adding a small delay fixes this issue. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Signed-off-by: David S. Miller <davem@davemloft.net> 2021-06-10MIPS: lantiq: Directly include linux/of.h in xway/dma.cMarc Zyngier This drivers currently obtains linux/of.h by luck and a chain of bizarre inclusions, which we're about to fix. Let's include the required file directly. Signed-off-by: Marc Zyngier <maz@kernel.org> 2020-08-17MIPS: lantiq: add missing GPHY clock aliases for ar10 and grx390Aleksander Jan Bajkowski Add missing GPHY clock aliases for ar10 (xrx300) and grx390 (xrx330). PMU in ar10 and grx390 differs from vr9. Ar10 has 3 and grx390 has 4 built-in GPHY compared to vr9 which has 2. Corespondings PMU bit: GPHY0 -> bit 29 GPHY1 -> bit 30 GPHY2 -> bit 31 GPHY3 -> bit 26 Tested on D-Link DWR-966 with OpenWRT. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Cc: linux-mips@vger.kernel.org Cc: john@phrozen.org Cc: hauke@hauke-m.de Cc: tsbogend@alpha.franken.de Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 2020-06-15MIPS: lantiq: xway: sysctrl: fix the GPHY clock alias namesMartin Blumenstingl The dt-bindings for the GSWIP describe that the node should be named "switch". Use the same name in sysctrl.c so the GSWIP driver can actually find the "gphy0" and "gphy1" clocks. Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Cc: stable@vger.kernel.org Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de> 2019-08-24MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driverMartin Blumenstingl The mainline PCIe PHY driver has it's own devicetree node. Update the clock alias so the mainline driver finds the clocks. The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300 and GRX390. The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and GRX390. The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390. Lantiq's board support package (called "UGW") names these registers "PDI". Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: john@phrozen.org Cc: kishon@ti.com Cc: ralf@linux-mips.org Cc: robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org Cc: hauke@hauke-m.de Cc: mark.rutland@arm.com Cc: ms@dev.tdt.de 2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333Thomas Gleixner Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 136 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.384967451@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-02-12MIPS: lantiq: pass struct device to DMA API functionsChristoph Hellwig The DMA API generally relies on a struct device to work properly, and only barely works without one for legacy reasons. Pass the easily available struct device from the platform_device to remedy this. Also use GFP_KERNEL instead of GFP_ATOMIC as the gfp_t for the memory allocation, as we aren't in interrupt context or under a lock. Note that this whole function looks somewhat bogus given that we never even look at the returned dma address, and the CPHYSADDR magic on a returned noncached mapping looks "interesting". But I'll leave that to people more familiar with the code to sort out. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: John Crispin <john@phrozen.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Sudip Mukherjee <sudipm.mukherjee@gmail.com> Cc: Felipe Balbi <balbi@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: dmaengine@vger.kernel.org Cc: netdev@vger.kernel.org Cc: linux-usb@vger.kernel.org Cc: linux-fbdev@vger.kernel.org Cc: alsa-devel@alsa-project.org Cc: iommu@lists.linux-foundation.org 2019-01-08cross-tree: phase out dma_zalloc_coherent()Luis Chamberlain We already need to zero out memory for dma_alloc_coherent(), as such using dma_zalloc_coherent() is superflous. Phase it out. This change was generated with the following Coccinelle SmPL patch: @ replace_dma_zalloc_coherent @ expression dev, size, data, handle, flags; @@ -dma_zalloc_coherent(dev, size, handle, flags) +dma_alloc_coherent(dev, size, handle, flags) Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org> [hch: re-ran the script on the latest tree] Signed-off-by: Christoph Hellwig <hch@lst.de>