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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2026-03-19 16:08:51 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2026-03-19 16:08:51 +0100
commit4aea1dc4cad17cd146072e13b1fd404f32b8b3ef (patch)
tree70991c25d188f5b1cd6f5d84f9f352ec2fa2effa /drivers/net/thunderbolt
parent224404f54036e33fe9968d1f69f29bf4bae0df7c (diff)
downloadkernel-linux-6.18.y.tar.gz
Linux 6.18.19linux-6.18.y
Link: https://lore.kernel.org/r/20260317162959.345812316@linuxfoundation.org Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Miguel Ojeda <ojeda@kernel.org> Tested-by: Jeffrin Jose T <jeffrin@rajagiritech.edu.in> Tested-by: Shung-Hsi Yu <shung-hsi.yu@suse.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Ron Economos <re@w6rz.net> Link: https://lore.kernel.org/r/20260318122621.714862892@linuxfoundation.org Tested-by: Brett A C Sheffield <bacs@librecast.net> Tested-by: Peter Schneider <pschneider1968@googlemail.com> Tested-by: Pavel Machek (CIP) <pavel@nabladev.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Ron Economos <re@w6rz.net> Tested-by: Wentao Guan <guanwentao@uniontech.com> Tested-by: Barry K. Nathan <barryn@pobox.com> Tested-by: Mark Brown <brooniekernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/net/thunderbolt')
0 files changed, 0 insertions, 0 deletions
span>cxl/test: Skip cxl_setup_parent_dport() for emulated dportsLi Ming 2024-02-16cxl/test: Add support for qos_class checkingDave Jiang 2024-01-22tools/testing/cxl: Disable "missing prototypes / declarations" warningsDan Williams 2023-12-22cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang 2023-12-04cxl: Add cxl_num_decoders_committed() usage to cxl_testDave Jiang 2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams 2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams 2023-06-25Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams 2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter 2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron 2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams 2023-02-14Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams 2023-02-14cxl/port: Export cxl_dvsec_rr_decode() to cxl_portDave Jiang 2023-01-05tools/testing/cxl: Prevent cxl_test from confusing production modulesDan Williams 2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams 2022-12-05Merge branch 'for-6.2/cxl-security' into for-6.2/cxlDan Williams 2022-12-03cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter 2022-11-30cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operationDave Jiang 2022-07-21cxl/region: Add region creation supportBen Widawsky 2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams 2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams 2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams 2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky 2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky 2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams 2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams 2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams 2022-02-08cxl/core/port: Rename bus.c to port.cDan Williams 2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams 2021-09-21tools/testing/cxl: Introduce a mock memory device + driverDan Williams 2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams