diff options
| author | Markus Niebel <Markus.Niebel@ew.tq-group.com> | 2025-12-16 14:39:25 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-04-02 13:25:53 +0200 |
| commit | c02419f1e56de8e16ec348b62458d30f7c2c6a83 (patch) | |
| tree | ca4eb32ec52e024e68e1666eeec3d4976038ec87 /arch/arm64 | |
| parent | b4737e26d4688b8aea88ad6ea4dbfeb6e78b0327 (diff) | |
arm64: dts: imx8mn-tqma8mqnl: fix LDO5 power off
commit 8adc841d43ebceabec996c9dcff6e82d3e585268 upstream.
Fix SD card removal caused by automatic LDO5 power off after boot
To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 13 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 22 |
2 files changed, 29 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index d7f7f9aafb7d..0d009f4be804 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -69,6 +69,10 @@ samsung,esc-clock-frequency = <20000000>; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MN_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; @@ -216,8 +220,7 @@ <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -226,8 +229,7 @@ <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -236,8 +238,7 @@ <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>, <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>, <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>, - <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>, - <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x84>; + <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>; }; pinctrl_usdhc2_gpio: usdhc2-gpiogrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 1d23814e11cd..e2ccebf6ee13 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -30,6 +30,20 @@ regulator-max-microvolt = <3300000>; }; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -233,6 +247,10 @@ vddio-supply = <&ldo3_reg>; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -287,6 +305,10 @@ fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc0>; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, |