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path: root/drivers/phy
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2023-08-22phy: qcom: Introduce M31 USB PHY driverVaradarajan Narayanan
Add the M31 USB2 phy driver for the USB M31 PHY (https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332 SoCs. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22phy: rockchip: inno-dsidphy: Add rv1126 supportJagan Teki
Add support for Rockchip RV1126 DSI-DPHY. The existing 2.5GHz phy timing table added for RK3568 is working as it is for RV1126 as well. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20230731110012.2913742-5-jagan@edgeble.ai Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22phy: amlogic: meson-g12a-usb2: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski
'soc_id' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-meson-g12a-usb2.c:322:17: error: cast to smaller integer type 'enum meson_soc_id' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230810091310.70231-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-11phy: marvell pxa-usb: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-pxa-usb.c:299:26: error: cast to smaller integer type 'enum pxa_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230810111958.205705-4-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-11phy: broadcom: sr-usb: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-bcm-sr-usb.c:314:13: error: cast to smaller integer type 'enum bcm_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230810111958.205705-3-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-11phy: broadcom: ns-usb3: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski
'family' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: drivers/phy/broadcom/phy-bcm-ns-usb3.c:209:17: error: cast to smaller integer type 'enum bcm_ns_family' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230810111958.205705-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-11phy: broadcom: sata: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-brcm-sata.c:775:19: error: cast to smaller integer type 'enum brcm_sata_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230810111958.205705-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-11phy: qcom: qmp-ufs: add missing offsets to sm8150 configurationDmitry Baryshkov
The conversion commit 7559e7572c03 ("phy: Explicitly include correct DT includes") misses offsets configuration for sm8150 (most likely it was developed separately from the series adding HS G4 support and was not adapted for the sm8150/sm8250 configuration split). Add missing offsets to sm8150_ufsphy_cfg. Fixes: 7559e7572c03 ("phy: Explicitly include correct DT includes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230731111009.3998089-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-04phy: realtek: usb: add the error handler for nvmem_cell_readStanley Chang
There are following smatch warning: drivers/phy/realtek/phy-rtk-usb2.c:901 get_phy_data_by_efuse() error: 'buf' dereferencing possible ERR_PTR() drivers/phy/realtek/phy-rtk-usb2.c:942 get_phy_data_by_efuse() error: 'buf' dereferencing possible ERR_PTR() drivers/phy/realtek/phy-rtk-usb3.c:460 get_phy_data_by_efuse() error: 'buf' dereferencing possible ERR_PTR() The nvmem_cell_read may fail to read. So, driver must handle failure cases. Fixes: 134e6d25f6bd ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY") Fixes: adda6e82a7de ("phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHY") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/linux-phy/e7ff2870-c30c-4d8d-a7a9-d2d6a4962eb5@kadam.mountain/ Signed-off-by: Stanley Chang <stanley_chang@realtek.com> Link: https://lore.kernel.org/r/20230801071509.20096-1-stanley_chang@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-31Merge 6.5-rc4 into usb-nextGreg Kroah-Hartman
We need the USB fixes in here for testing and for other patches to be applied on top of. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-30phy: realtek: usb: phy-rtk-usb2 and phy-rtk-usb3 needs USB_COMMONStanley Chang
When USB_COMMON are not enabled, phy-rtk-usb2 and phy-rtk-usb3 suffers a build error due to a missing usb_debug_root that is provided by CONFIG_USB_COMMON, so make the driver select USB_COMMON. or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb2.o: in function `create_phy_debug_root': >> drivers/phy/realtek/phy-rtk-usb2.c:715: undefined reference to `usb_debug_root' >> or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb2.c:715: undefined reference to `usb_debug_root' or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb3.o: in function `create_phy_debug_root': >> drivers/phy/realtek/phy-rtk-usb3.c:349: undefined reference to `usb_debug_root' >> or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb3.c:349: undefined reference to `usb_debug_root' Fixes: 134e6d25f6bd ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY") Fixed: adda6e82a7de ("phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHY") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307290733.weSlHrGp-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202307291022.3pVeTR9z-lkp@intel.com/ Signed-off-by: Stanley Chang <stanley_chang@realtek.com> Link: https://lore.kernel.org/r/20230729053029.6226-1-stanley_chang@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-26phy: starfive: StarFive PHYs should depend on ARCH_STARFIVEGeert Uytterhoeven
The various StarFive PHYs are only present on StarFive SoCs. Hence add a dependency on ARCH_STARFIVE, to prevent asking the user about these drivers when configuring a kernel without StarFive SoC support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/12097f6107a18e2f7cfb80f47ac7b27808e062c4.1690300076.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-26phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHYStanley Chang
Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB controller. Added the driver to drive the USB 3.0 PHY transceivers. Signed-off-by: Stanley Chang <stanley_chang@realtek.com> Link: https://lore.kernel.org/r/20230725033318.8361-3-stanley_chang@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-26phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHYStanley Chang
Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB controller. Added the driver to drive the USB 2.0 PHY transceivers. Signed-off-by: Stanley Chang <stanley_chang@realtek.com> Link: https://lore.kernel.org/r/20230725033318.8361-2-stanley_chang@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-07-25phy: starfive: make phys depend on HAS_IOMEMVinod Koul
the startfive phy drivers use devm_platform_ioremap_resource() which on some archs (s390) is not present. So make the drivers depend on HAS_IOMEM Fixes: f8aa660841bc ("phy: starfive: Add mipi dphy rx support") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307250509.oeudxG28-lkp@intel.com/ Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230725063856.482696-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-24phy: qcom-qmp-combo: add qcom,sc7280-qmp-usb3-dp-phy compat entryDmitry Baryshkov
Add separate device entry for Combo USB+DP QMP PHY on sc7280 platform. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711120916.4165894-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-24phy: qcom-qmp-combo: populate offsets for all combo PHYsDmitry Baryshkov
In order to support newer style bindings for combo PHYs, populate offsets for all Combo QMP PHY configurations. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711120916.4165894-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-24phy: qcom-qmp-combo: simplify clock handlingDmitry Baryshkov
For the existing PHYs for new binding we are going to drop ref_clk_src clock and always use ref clock. Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional() when new bindings are used and devm_clk_bulk_get_all() when legacy bindings are in place. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711120916.4165894-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-24phy: Remove duplicated include in xusb.cYang Li
./drivers/phy/tegra/xusb.c: linux/platform_device.h is included more than once. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5930 Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230719003614.5506-1-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-24phy: hisilicon: Fix an out of bounds check in hisi_inno_phy_probe()Harshit Mogalapalli
The size of array 'priv->ports[]' is INNO_PHY_PORT_NUM. In the for loop, 'i' is used as the index for array 'priv->ports[]' with a check (i > INNO_PHY_PORT_NUM) which indicates that INNO_PHY_PORT_NUM is allowed value for 'i' in the same loop. This > comparison needs to be changed to >=, otherwise it potentially leads to an out of bounds write on the next iteration through the loop Fixes: ba8b0ee81fbb ("phy: add inno-usb2-phy driver for hi3798cv200 SoC") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Link: https://lore.kernel.org/r/20230721090558.3588613-1-harshit.m.mogalapalli@oracle.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-24phy: starfive: Add mipi dphy rx supportChanghuang Liang
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Minda Chen <minda.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230718070803.16660-3-changhuang.liang@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-24phy: starfive: fix error code in probeDan Carpenter
This is using the wrong pointer, "phy->regs" vs "phy->phy". Fixes: fd097f48eea9 ("phy: starfive: Add JH7110 PCIE 2.0 PHY driver") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/3cc81f2a-efd7-4ef7-ae6b-e38c91efe153@moroto.mountain Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-18phy: qcom-qmp-pcie: add support for sa8775pMrinmay Sarkar
Add support for dual and four lane PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689311319-22054-5-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-17phy: Explicitly include correct DT includesRob Herring
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-14phy: ti: gmii-sel: Allow parent to not be syscon nodeAndrew Davis
If the parent node is not a syscon type, then fallback and check if we can get a regmap from our own node. This no longer forces us to make the parent of this node a syscon node when that might not be appropriate. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20230713200957.134480-1-afd@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: zynqmp: Allow variation in refclk rateSean Anderson
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom-qmp-ufs: populate offsets configurationDmitry Baryshkov
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230711145153.4167820-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: starfive: Add JH7110 PCIE 2.0 PHY driverMinda Chen
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-5-minda.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: starfive: Add JH7110 USB 2.0 PHY driverMinda Chen
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-4-minda.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> Signed-off-by: Marcin Wierzbicki <mawierzb@cisco.com> Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: add more supported pre-pll ratesAlex Bee
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: force set_rate on power_onHuicong Xu
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu <xhc@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-6-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg writeJonas Karlman
inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-5-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rateJonas Karlman
no_c is not used in any calculation, lets remove it. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-4-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rateZheng Yang
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found in the pre pll config table when the fractal divider is used. This can prevent proper power_on because a tmdsclock for the new rate is not found in the pre pll config table. Fix this by saving and returning a rounded pixel rate that exist in the pre pll config table. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Zheng Yang <zhengyang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-3-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy/rockchip: inno-hdmi: use correct vco_div_5 macro on rk3328Jonas Karlman
inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro when configuring vco_div_5 on RK3328. Fix this by using correct vco_div_5 macro for RK3328. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-2-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom: qmp-combo: extract common function to setup clocksDmitry Baryshkov
Extact qmp_combo_configure_dp_clocks(), a common function to setup PHY clocks depending on the selected link rate. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom: qmp-combo: drop qmp_v6_dp_aux_init()Dmitry Baryshkov
The only difference between qmp_v6_dp_aux_init() and qmp_v4_dp_aux_init() is the address of COM_BIAS_EN_CLKBUFLR_EN register. Move it to register layout and drop the duplicate function. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom: qmp-combo: drop similar functionsDmitry Baryshkov
The functions qmp_v5_configure_dp_phy() and qmp_v6_configure_dp_phy() are now copies of qmp_v4_configure_dp_phy(). Drop them and use the v4 function in all the cases. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for some more registersDmitry Baryshkov
Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN registers. This will allow us to unify qmp_v[456]_configure_dp_phy() functions in the next commit. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for even more registersDmitry Baryshkov
Instead of passing additional registers to qmp_combo_configure_dp_swing(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom: qmp-combo: reuse register layouts for more registersDmitry Baryshkov
Instead of passing additional registers to qmp_v456_configure_dp_phy(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom: qmp-combo: correct bias0_en programmingDmitry Baryshkov
It seems the commit a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") contained a typo for selecting bias0_en values. First, bias0_en and bias1_en are expected to be symmetrical, and then the vendor driver also uses `flipped : 0x3E : 0x15` statement for bias0_en. Correct bias0_en programming to follow this. Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550") Fixes: a2e927b0e50d ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230621153317.1025914-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: xilinx: phy-zynqmp: dynamic clock support for power-savePiyush Mehta
Enabling clock for all the lanes consumes power even PHY is active or inactive. To resolve this, enable/disable clocks in phy_init/phy_exit. By default clock is disabled for all the lanes. Whenever phy_init called from USB, SATA, or display driver, etc. It enabled the required clock for requested lane. On phy_exit cycle, it disabled clock for the active PHYs. During the suspend/resume cycle, each USB/ SATA/ display driver called phy_exit/phy_init individually. It disabled clock on exit, and enabled on initialization for the active PHYs. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Link: https://lore.kernel.org/r/20230613140250.3018947-3-piyush.mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: xilinx: add runtime PM supportPiyush Mehta
Added Runtime power management support to the xilinx phy driver and using DEFINE_RUNTIME_DEV_PM_OPS new macros allows the compiler to remove the unused dev_pm_ops structure and related functions if !CONFIG_PM without the need to mark the functions __maybe_unused. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Link: https://lore.kernel.org/r/20230613140250.3018947-2-piyush.mehta@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: mediatek: mipi-dsi: Compress of_device_id match entriesAngeloGioacchino Del Regno
All of the entries do fit in a maximum of 82 columns, which is acceptable. While at it, also remove the useless comma on the last entry and add the usual sentinel comment. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230525115258.90091-4-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: mediatek: mipi-dsi: Use devm variant for of_clk_add_hw_provider()AngeloGioacchino Del Regno
Switch to devm_of_clk_add_hw_provider() in the probe function: this also allows to entirely remove the .remove_new() callback, as its only task was to unregister the clock provider. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230525115258.90091-3-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: mediatek: mipi-dsi: Convert to register clk_hwAngeloGioacchino Del Regno
Instead of registering a struct clk, directly register clk_hw: this allows us to cleanup a pointer to struct clk from struct mtk_mipi_tx. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230525115258.90091-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom-qmp-usb: split off the legacy USB+dp_com supportDmitry Baryshkov
When adding support for some of the platforms (sc7180, sc8180x, sdm845, sm8[1234]50), we added USB PHYs for the combo USB+DP QMP PHYs. Now all such usecases were migrated to use USB+DP Combo driver. To simplify the qcom-qmp-usb PHY driver split the legacy USB+dp_com support into a separate driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230531023415.1209301-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: qcom-qmp-combo: add support for the USB+DP PHY on SM8150 platformDmitry Baryshkov
SM8150 and SC8180X are close relatives. Reuse sc8180x data to support USB+DP combo PHY on SM8150 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230531023415.1209301-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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