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2025-11-14Merge tag 'drm-misc-fixes-2025-11-13' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes Short summary of fixes pull: client: - Fix description of module parameter panthor: - Flush writes before mapping buffers vmwgfx: - Improve command validation - Improve ref counting - Fix cursor-plane support Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251113132317.GA451885@linux.fritz.box
2025-11-14drm/msm/dpu: support plane splitting in quad-pipe caseJun Nie
The content of every half of screen is sent out via one interface in dual-DSI case. The content for every interface is blended by a LM pair in quad-pipe case, thus a LM pair should not blend any content that cross the half of screen in this case. Clip plane into pipes per left and right half screen ROI if topology is quad pipe case. The clipped rectangle on every half of screen is futher handled by two pipes if its width exceeds a limit for a single pipe. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/675416/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-9-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: support SSPP assignment for quad-pipe caseJun Nie
Currently, SSPPs are assigned to a maximum of two pipes. However, quad-pipe usage scenarios require four pipes and involve configuring two stages. In quad-pipe case, the first two pipes share a set of mixer configurations and enable multi-rect mode when certain conditions are met. The same applies to the subsequent two pipes. Assign SSPPs to the pipes in each stage using a unified method and to loop the stages accordingly. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/675414/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-8-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: blend pipes per mixer pairs configJun Nie
Currently, only 2 pipes are used at most for a plane. A stage structure describes the configuration for a mixer pair. So only one stage is needed for current usage cases. The quad-pipe case will be added in future and 2 stages are used in the case. So extend the stage to an array with array size STAGES_PER_PLANE and blend pipes per mixer pair with configuration in the stage structure. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675412/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-7-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: Use dedicated WB number definitionJun Nie
Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are supported at most in one encoder. The case of 4 channels per encoder is to be added. To avoid breaking current WB usage case, use dedicated WB definition before 4 WB usage case is supported in future. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675410/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-6-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixerJun Nie
The stage contains configuration for a mixer pair. Currently the plane supports just one stage and 2 pipes. Quad-pipe support will require handling 2 stages and 4 pipes at the same time. In preparation for that add a separate define, PIPES_PER_PLANE, to denote number of pipes that can be used by the plane. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675408/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-5-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: handle pipes as arrayJun Nie
There are 2 pipes in a drm plane at most currently, while 4 pipes are required for quad-pipe case. Generalize the handling to pipe pair and ease handling to another pipe pair later. Store pipes in array with removing dedicated r_pipe. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675406/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-4-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: Add pipe as trace argumentJun Nie
Add pipe as trace argument in trace_dpu_crtc_setup_mixer() to ease converting pipe into pipe array later. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675404/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-3-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: bind correct pingpong for quad pipeJun Nie
There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd interface to 3rd PP instead of the 2nd PP. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675402/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-2-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: fix mixer number counter on allocationJun Nie
Current code only supports usage cases with one pair of mixers at most. To support quad-pipe usage case, two pairs of mixers need to be reserved. The lm_count for all pairs is cleared if a peer allocation fails in current implementation. Reset the current lm_count to an even number instead of completely clearing it. This prevents all pairs from being cleared in cases where multiple LM pairs are needed. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/675400/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-1-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: Remove dead-code in dpu_encoder_helper_reset_mixers()Christophe JAILLET
'mixer' is only zeroed and is not use. Remove it. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-By: Mahesh Bharadwaj Kannan <mahesh.kannan@oss.qualcomm.com> Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw blocks") Patchwork: https://patchwork.freedesktop.org/patch/679854/ Link: https://lore.kernel.org/r/8e3b2fbbf5440aa219feb667f5423c7479eb2656.1760040536.git.christophe.jaillet@wanadoo.fr Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14gpu: nova-core: Set correct DMA maskAlistair Popple
Set the correct DMA mask. Without this DMA will fail on some setups. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-2-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: compute layout of more framebuffer regions required for GSPAlexandre Courbot
Compute more of the required FB layout information to boot the GSP firmware. This information is dependent on the firmware itself, so first we need to import and abstract the required firmware bindings in the `nvfw` module. Then, a new FB HAL method is introduced in `fb::hal` that uses these bindings and hardware information to compute the correct layout information. This information is then used in `fb` and the result made visible in `FbLayout`. These 3 things are grouped into the same patch to avoid lots of unused warnings that would be tedious to work around. As they happen in different files, they should not be too difficult to track separately. Acked-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-1-8ae4058e3c0e@nvidia.com>
2025-11-13drm/xe/oa: Store forcewake reference in stream structureMatt Roper
Calls to xe_force_wake_put() should generally pass the exact reference returned by xe_force_wake_get(). Since OA grabs and releases forcewake in different functions, xe_oa_stream_destroy() is currently calling put with a hardcoded ALL mask. Although this works for now, it's somewhat fragile in case OA moves to more precise power domain management in the future. Stash the original reference obtained during stream initialization inside the stream structure so that we can use it directly when the stream is destroyed. Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Link: https://patch.msgid.link/20251110232017.1475869-35-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-13drm/xe/eustall: Store forcewake reference in stream structureMatt Roper
Calls to xe_force_wake_put() should generally pass the exact reference returned by xe_force_wake_get(). Since EU stall grabs and releases forcewake in different functions, xe_eu_stall_disable_locked() is currently calling put with a hardcoded RENDER domain. Although this works for now, it's somewhat fragile in case the power domain(s) required by stall sampling change in the future, or if workarounds show up that require us to obtain additional domains. Stash the original reference obtained during stream enable inside the stream structure so that we can use it directly when the stream is disabled. Cc: Harish Chegondi <harish.chegondi@intel.com> Reviewed-by: Harish Chegondi <harish.chegondi@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patch.msgid.link/20251110232017.1475869-34-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-13drm/xe/forcewake: Improve kerneldocMatt Roper
Improve the kerneldoc for forcewake a bit to give more detail about what the structures represent. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Stuart Summers <stuart.summers@intel.com> Link: https://patch.msgid.link/20251110232017.1475869-33-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-13drm/imx/ipuv3: Fix dumb-buffer allocation for non-RGB formatsThomas Zimmermann
Align pitch to multiples of 8 pixels for bpp values that do not map to RGB formats. The call to drm_driver_color_mode_format() fails with DRM_INVALID_FORMAT in these cases. Fall back to manually computing the pitch alignment from which drm_mode_size_dumb() can compute the correct pitch. Fixes userspace that allocates dumb buffers for YUV formats, where bpp equals 12. A common example is the IGT kms_getfb test. v2: - ignore width in calculation Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: b1d0e470f881 ("drm/imx/ipuv3: Compute dumb-buffer sizes with drm_mode_size_dumb()") Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patch.msgid.link/20251104153832.189666-1-tzimmermann@suse.de
2025-11-13drm/xe/pf: Use migration-friendly GGTT auto-provisioningMichal Wajdeczko
Instead of trying very hard to find the largest fair GGTT size that could be allocated for VFs on the current tile, pick some smaller rounded down to power-of-two value that is more likely to be provisioned in the same manner by the other PF instance: num VFs | GGTT space (MiB) --------+----------------- 63..57 | 56 56..29 | 64 28..15 | 128 14..8 | 256 7..4 | 512 3..2 | 1024 1 | 2048 (regular PF) 1 | 3584 (admin only PF) Note that due to FW/HW limitations we can't share all 4GiB GGTT address space with VFs, so for the larger (>7) number of the VFs the change in the outcome is happening at different points than we have in case of GuC contexts/doorbells IDs. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251112124408.8094-1-michal.wajdeczko@intel.com
2025-11-13drm/client: fix MODULE_PARM_DESC string for "active"Randy Dunlap
The MODULE_PARM_DESC string for the "active" parameter is missing a space and has an extraneous trailing ']' character. Correct these. Before patch: $ modinfo -p ./drm_client_lib.ko active:Choose which drm client to start, default isfbdev] (string) After patch: $ modinfo -p ./drm_client_lib.ko active:Choose which drm client to start, default is fbdev (string) Fixes: f7b42442c4ac ("drm/log: Introduce a new boot logger to draw the kmsg on the screen") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251112010920.2355712-1-rdunlap@infradead.org
2025-11-13drm/xe/pf: Add wait helper for VF FLRMichał Winiarski
VF FLR requires additional processing done by PF driver. The processing is done after FLR is already finished from PCIe perspective. In order to avoid a scenario where migration state transitions while PF processing is still in progress, additional synchronization point is needed. Add a helper that will be used as part of VF driver struct pci_error_handlers .reset_done() callback. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-24-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Handle VRAM migration data as part of PF controlMichał Winiarski
Connect the helpers to allow save and restore of VRAM migration data in stop_copy / resume device state. Co-developed-by: Lukasz Laguna <lukasz.laguna@intel.com> Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251112132220.516975-23-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/migrate: Add function to copy of VRAM data in chunksLukasz Laguna
Introduce a new function to copy data between VRAM and sysmem objects. The existing xe_migrate_copy() is tailored for eviction and restore operations, which involves additional logic and operates on entire objects. The xe_migrate_vram_copy_chunk() allows copying chunks of data to or from a dedicated buffer object, which is essential in case of VF migration. Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251112132220.516975-22-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Add helper to retrieve VF's LMEM objectLukasz Laguna
Instead of accessing VF's lmem_obj directly, introduce a helper function to make the access more convenient. Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-21-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Handle MMIO migration data as part of PF controlMichał Winiarski
Implement the helpers and use them for save and restore of MMIO migration data in stop_copy / resume device state. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-20-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Handle GGTT migration data as part of PF controlMichał Winiarski
Connect the helpers to allow save and restore of GGTT migration data in stop_copy / resume device state. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-19-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Add helpers for VF GGTT migration data handlingMichał Winiarski
In an upcoming change, the VF GGTT migration data will be handled as part of VF control state machine. Add the necessary helpers to allow the migration data transfer to/from the HW GGTT resource. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-18-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Handle GuC migration data as part of PF controlMichał Winiarski
Connect the helpers to allow save and restore of GuC migration data in stop_copy / resume device state. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-17-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Switch VF migration GuC save/restore to struct migration dataMichał Winiarski
In upcoming changes, the GuC VF migration data will be handled as part of separate SAVE/RESTORE states in VF control state machine. Now that the data is decoupled from both guc_state debugfs and PAUSE state, we can safely remove the struct xe_gt_sriov_state_snapshot and modify the GuC save/restore functions to operate on struct xe_sriov_migration_data. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-16-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Don't save GuC VF migration data on pauseMichał Winiarski
In upcoming changes, the GuC VF migration data will be handled as part of separate SAVE/RESTORE states in VF control state machine. Remove it from PAUSE state. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-15-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Remove GuC migration data save/restore from GT debugfsMichał Winiarski
In upcoming changes, SR-IOV VF migration data will be extended beyond GuC data and exported to userspace using VFIO interface (with a vendor-specific variant driver) and a device-level debugfs interface. Remove the GT-level debugfs. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-14-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Increase PF GuC Buffer Cache size and use it for VF migrationMichał Winiarski
Contiguous PF GGTT VMAs can be scarce after creating VFs. Increase the GuC buffer cache size to 8M for PF so that we can fit GuC migration data (which currently maxes out at just over 4M) and use the cache instead of allocating fresh BOs. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-13-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe: Allow the caller to pass guc_buf_cache sizeMichał Winiarski
An upcoming change will use GuC buffer cache as a place where GuC migration data will be stored, and the memory requirement for that is larger than indirect data. Allow the caller to pass the size based on the intended usecase. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-12-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe: Add sa/guc_buf_cache sync interfaceMichał Winiarski
In upcoming changes the cached buffers are going to be used to read data produced by the GuC. Add a counterpart to flush, which synchronizes the CPU-side of suballocation with the GPU data and propagate the interface to GuC Buffer Cache. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-11-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Expose VF migration data size over debugfsMichał Winiarski
The size is normally used to make a decision on when to stop the device (mainly when it's in a pre_copy state). Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-10-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Add minimalistic migration descriptorMichał Winiarski
The descriptor reuses the KLV format used by GuC and contains metadata that can be used to quickly fail migration when source is incompatible with destination. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-9-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Add support for encap/decap of bitstream to/from packetMichał Winiarski
Add debugfs handlers for migration state and handle bitstream .read()/.write() to convert from bitstream to/from migration data packets. As descriptor/trailer are handled at this layer - add handling for both save and restore side. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-8-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Add helpers for migration data packet allocation / freeMichał Winiarski
Now that it's possible to free the packets - connect the restore handling logic with the ring. The helpers will also be used in upcoming changes that will start producing migration data packets. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-7-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Add data structures and handlers for migration ringsMichał Winiarski
Migration data is queued in a per-GT ptr_ring to decouple the worker responsible for handling the data transfer from the .read() and .write() syscalls. Add the data structures and handlers that will be used in future commits. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-6-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Add save/restore control state stubs and connect to debugfsMichał Winiarski
The states will be used by upcoming changes to produce (in case of save) or consume (in case of resume) the VF migration data. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-5-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Convert control state to bitmapMichał Winiarski
In upcoming changes, the number of states will increase as a result of introducing SAVE and RESTORE states. This means that using unsigned long as underlying storage won't work on 32-bit architectures, as we'll run out of bits. Use bitmap instead. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202510231918.XlOqymLC-lkp@intel.com/ Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-4-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe: Move migration support to device-level structMichał Winiarski
Upcoming changes will allow users to control VF state and obtain its migration data with a device-level granularity (not tile/gt). Change the data structures to reflect that and move the GT-level migration init to happen after device-level init. Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-3-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/xe/pf: Remove GuC version check for migration supportMichał Winiarski
Since commit 4eb0aab6e4434 ("drm/xe/guc: Bump minimum required GuC version to v70.29.2"), the minimum GuC version required by the driver is v70.29.2, which should already include everything that we need for migration. Remove the version check. Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-2-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2025-11-13drm/i915/display: Add default case to mipi_exec_send_packetJonathan Cavitt
Add a default case to the switch case statement in mipi_exec_send_packet to prevent attempts to read an uninitialized ret value. It's unlikely the default case will ever occur during regular exeuction, but if more MIPI DSI Processor-to-Peripheral transaction types are ever added, then having this in place will be a useful safety guard. Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Fixes: 23db1577ce2d ("drm/i915/dsi: log send packet sequence errors") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20251104164150.16795-2-jonathan.cavitt@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-13drm/xe: remove stale runtime_pm memberJani Nikula
This has become unused and unnecessary. Remove. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20251112185547.172113-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-13drm/i915/ltphy: include intel_display_utils.h instead of i915_utils.hJani Nikula
Display code stopped using i915_utils.h in favour of intel_display_utils.h. Fix recent additions. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20251112181342.107911-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-12drm/xe/guc: Eliminate RPa frequency cachingSk Anirban
Remove the cached pc->rpa_freq field and refactor RPA frequency handling to fetch values directly from hardware registers on each request. v2: Check graphics version instead of platform (Rodrigo) v3: Fix graphics version check (Badal) Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Suggested-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Sk Anirban <sk.anirban@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20251112185153.3593145-6-sk.anirban@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-11-12drm/xe/guc: Eliminate RPe caching for SLPC parameter handlingSk Anirban
RPe is runtime-determined by PCODE and caching it caused stale values, leading to incorrect GuC SLPC parameter settings. Drop the cached rpe_freq field and query fresh values from hardware on each use to ensure GuC SLPC parameters reflect current RPe. v2: Remove cached RPe frequency field (Rodrigo) v3: Remove extra variable (Vinay) Modify function name (Vinay) v4: Maintain a separate function for PVC (Rodrigo) v5: Avoid RPn update while fetching RPe frequency (Rodrigo) v6: Split platform-specific RPe comments (Vinay) Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/5166 Signed-off-by: Sk Anirban <sk.anirban@intel.com> Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20251112185153.3593145-5-sk.anirban@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-11-12vfio/gvt: Convert to get_region_info_capsJason Gunthorpe
Remove the duplicate code and change info to a pointer. Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/17-v2-2a9e24d62f1b+e10a-vfio_get_region_info_op_jgg@nvidia.com Signed-off-by: Alex Williamson <alex@shazbot.org>
2025-11-12vfio/gvt: Provide a get_region_info opJason Gunthorpe
Move it out of intel_vgpu_ioctl() and re-indent it. Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/13-v2-2a9e24d62f1b+e10a-vfio_get_region_info_op_jgg@nvidia.com Signed-off-by: Alex Williamson <alex@shazbot.org>
2025-11-12drm/i915/cursor: Initialize 845 vs 865 cursor size separatelyVille Syrjälä
The if+ternary combo used for the max cursor width initialization on 845/865 is rather cumbersome. Just split this into a straight up if ladder. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251107181126.5743-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-17 18:31:30 +0000