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2025-11-19drm/xe/pm: Add scope-based cleanup helper for runtime PMMatt Roper
Add a scope-based helpers for runtime PM that may be used to simplify cleanup logic and potentially avoid goto-based cleanup. For example, using guard(xe_pm_runtime)(xe); will get runtime PM and cause a corresponding put to occur automatically when the current scope is exited. 'xe_pm_runtime_noresume' can be used as a guard replacement for the corresponding 'noresume' variant. There's also an xe_pm_runtime_ioctl conditional guard that can be used as a replacement for xe_runtime_ioctl(): ACQUIRE(xe_pm_runtime_ioctl, pm)(xe); if ((ret = ACQUIRE_ERR(xe_pm_runtime_ioctl, &pm)) < 0) /* failed */ In a few rare cases (such as gt_reset_worker()) we need to ensure that runtime PM is dropped when the function is exited by any means (including error paths), but the function does not need to acquire runtime PM because that has already been done earlier by a different function. For these special cases, an 'xe_pm_runtime_release_only' guard can be used to handle the release without doing an acquisition. These guards will be used in future patches to eliminate some of our goto-based cleanup. v2: - Specify success condition for xe_pm runtime_ioctl as _RET >= 0 so that positive values will be properly identified as success and trigger destructor cleanup properly. v3: - Add comments to the kerneldoc for the existing 'get' functions indicating that scope-based handling should be preferred where possible. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patch.msgid.link/20251118164338.3572146-31-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-19drm/xe/forcewake: Add scope-based cleanup for forcewakeMatt Roper
Since forcewake uses a reference counting get/put model, there are many places where we need to be careful to drop the forcewake reference when bailing out of a function early on an error path. Add scope-based cleanup options that can be used in place of explicit get/put to help prevent mistakes in this area. Examples: CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); Obtain forcewake on the XE_FW_GT domain and hold it until the end of the current block. The wakeref will be dropped automatically when the current scope is exited by any means (return, break, reaching the end of the block, etc.). xe_with_force_wake(fw_ref, gt_to_fw(ss->gt), XE_FORCEWAKE_ALL) { ... } Hold all forcewake domains for the following block. As with the CLASS usage, forcewake will be dropped automatically when the block is exited by any means. Use of these cleanup helpers should allow us to remove some ugly goto-based error handling and help avoid mistakes in functions with lots of early error exits. An 'xe_force_wake_release_only' class is also added for cases where a forcewake reference is passed in from another function and the current function is responsible for releasing it in every flow and error path. v2: - Create a separate constructor that just wraps xe_force_wake_get for use in the class. This eliminates the need to update the signature of xe_force_wake_get(). (Michal) v3: - Wrap xe_with_force_wake's 'done' marker in __UNIQUE_ID. (Gustavo) - Add a note to xe_force_wake_get()'s kerneldoc explaining that scope-based cleanup is preferred when possible. (Gustavo) - Add an xe_force_wake_release_only class. (Gustavo) v4: - Add NULL check on fw in release_only variant. (Gustavo) Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patch.msgid.link/20251118164338.3572146-30-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-19drm/plane: Fix create_in_format_blob() return valueVille Syrjälä
create_in_format_blob() is either supposed to return a valid pointer or an error, but never NULL. The caller will dereference the blob when it is not an error, and thus will oops if NULL returned. Return proper error values in the failure cases. Cc: stable@vger.kernel.org Cc: Arun R Murthy <arun.r.murthy@intel.com> Fixes: 0d6dcd741c26 ("drm/plane: modify create_in_formats to acommodate async") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251112233030.24117-2-ville.syrjala@linux.intel.com Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
2025-11-19drm/xe/rps: build RPS as part of xeJani Nikula
Reduce the conditional compilation in i915 by building intel_display_rps.c as part of the xe module. This doesn't actually enable RPS on xe, because there's no parent interface implementation on xe side, but it's a step in the right direction. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/93df0bb727fce14aa9a542dbd2c0826a0fa0a16f.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915: add .fence_priority_display to parent interfaceJani Nikula
Add .fence_priority_display() to display parent interface, removing a display dependency on gem/i915_gem_object.h. This allows us to remove the xe compat gem/i915_gem_object.h. v2: Don't mix this with the rps interface (Ville) v3: Rebase Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/c7782862956e3aa59eaeb6dcf80906c1fc063ae1.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915/rps: postpone i915 fence check to boostJani Nikula
Make the RPS boost code independent of i915 request code by moving the dma_fence_is_i915() check to the RPS boost call. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/2653395523ee04c9ca3216f197f08c25a9f7716d.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915/rps: call RPS functions via the parent interfaceJani Nikula
Add struct intel_display_rps_interface to the display parent interface, and call the RPS functions through it. The RPS interface is optional. v2: s/boost/boost_if_not_started/ and keep comment in caller (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/6a6c4420d9f2d9a545ee6df4cad5fdc32a86636b.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915/rps: store struct dma_fence in struct wait_rps_boostJani Nikula
Prefer the more generic pointer rather than i915 specific data type. Also use dma_fence_put() for symmetry with the dma_fence_get() Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/950948ae6d3d5fbc4af3401ea77e609945b73a77.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915: add .has_fenced_regions to parent interfaceJani Nikula
Add .has_fenced_regions() to display parent interface, removing more dependencies on struct drm_i915_private, i915_drv.h, and gt/intel_gt_types.h. This allows us to remove the xe compat gt/intel_gt_types.h. v2: s/fence_support_legacy/has_fenced_regions/ (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/309f61a8742c3bf731c820b2f9e1024143db8598.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915: add .vgpu_active to parent interfaceJani Nikula
Add .vgpu_active() to display parent interface, removing more dependencies on struct drm_i915_private, i915_drv.h, and i915_vgpu.h. This also allows us to remove the xe compat i915_vgpu.h. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/a2d4043ebaaf8f69bb738d5d1332afd2847550ad.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/{i915,xe}/display: move irq calls to parent interfaceJani Nikula
Add an irq parent driver interface for the .enabled and .synchronize calls. This lets us drop the dependency on i915_drv.h and i915_irq.h in multiple places, and subsequently remove the compat i915_irq.h and i915_irq.c files along with the display/ext directory from xe altogether. Introduce new intel_parent.[ch] as the wrapper layer to chase the function pointers and convert between generic and more specific display types. v2: Keep static wrappers in intel_display_irq.c (Ville) v3: Full blown wrappers in intel_parent.[ch] (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/dd62dd52ef10d9ecf77da3bdf6a70f71193d141c.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915/display: convert the display irq interfaces to struct intel_displayJani Nikula
Convert the irq/error init/reset interfaces from struct intel_uncore to struct intel_display, and drop the dependency on intel_uncore.h. Since the intel_de_*() calls handle the DMC wakelock internally, we can drop the wrappers handling wakelocks completely. v2: Drop the wakelock wrappers (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/710e03906da91244208839b357fe9171e37441ba.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/{i915, xe}/display: duplicate gen2 irq/error init/reset in display irqJani Nikula
Duplicate gen2_irq_reset(), gen2_assert_iir_is_zero(), gen2_irq_init(), gen2_error_reset(), and gen2_error_init() in intel_display_irq.c. This allows us to drop the duplicates from xe, and prepares for future cleanups. Although duplication is undesirable in general, in this case the local duplicates lead to a cleaner end result. There's a slight wrinkle in gen2_assert_iir_is_zero(). We need to use non-device based logging until we pass in struct intel_display in a separate change. v2: - Keep xe compat stuff due to series reorder and rebase - Keep the WARN as regular WARN - Rename the functions in the same go Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/296d74731cce57ab7534c57969d3146294adda57.1763370931.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915/dram: Fix ICL DIMM_S decodingVille Syrjälä
Unfortunately the MAD_DIMM DIMM_S and DIMM_L bits on ICL are not idential, so we are currently decoding DIMM_S incorrectly. Fix the problem by defining the DIMM_S and DIMM_L bits separately. And for consistency do that same for SKL, even though there the bits do match between the two DIMMs. The result is rather repetitive in places, but I didn't feel like obfuscatign things with cpp macros/etc. Broken decoding on Dell XPS 13 7390 2-in-1: CH0 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 DIMM S size: 32 Gb, width: X32, ranks: 3, 16Gb+ DIMMs: no CH0 ranks: 2, 16Gb+ DIMMs: no CH1 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 DIMM S size: 32 Gb, width: X32, ranks: 3, 16Gb+ DIMMs: no CH1 ranks: 2, 16Gb+ DIMMs: no Memory configuration is symmetric? no Fixed decoding on Dell XPS 13 7390 2-in-1: CH0 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 DIMM S size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH0 ranks: 2, 16Gb+ DIMMs: no CH1 DIMM L size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 DIMM S size: 32 Gb, width: X16, ranks: 2, 16Gb+ DIMMs: no CH1 ranks: 2, 16Gb+ DIMMs: no Memory configuration is symmetric? yes Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029204215.12292-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-11-19drm/i915/dram: Sort SKL+ DIMM register bitsVille Syrjälä
Use the customary big endian order when defining the SKL/ICL DIMM registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029204215.12292-3-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-11-19drm/i915/dram: Use REG_GENMASK() & co. for the SKL+ DIMM regsVille Syrjälä
Modernize the SKL/ICL DIMM registers with REG_GENMASK() & co. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251029204215.12292-2-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-11-19drm/panel: sofef00: Non-continuous mode and video burst are supportedDavid Heidelberg
The panel supports both modes. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-12-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Mark the LPM mode always-onDavid Heidelberg
The panel operated in low-power mode, with exception of changing the brightness levels. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-11-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Simplify get_modesDavid Heidelberg
Levearage drm_connector_helper_get_modes_fixed helper function. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-10-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Introduce compatible which includes the panel nameDavid Heidelberg
Compatible should correspond to the panel used and the driver currently supports only AMS628NW01 panel. Adapt the internal driver structures to reflect the name. Original, not very descriptive, compatible is kept to ensure compatibility with older device-trees. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-9-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Initialise at 50% brightnessCasey Connolly
Initialising at max brightness is not necessary. Half brightness is much more comfortable. Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-8-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Add prepare_prev_first flag to drm_panelCasey Connolly
This corrects the host initialisation sequence so that we can send DSI/DCS commands in prepare(). Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-7-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Introduce page macroDavid Heidelberg
Introducing the macro make the code a bit clearer. Looking at other Samsung drivers, I assume it's lvl2, thou due to not available documentation it's only educated guess. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-6-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Split sending commands to the enable/disable functionsDavid Heidelberg
It's not possible to send DSI panel commands in the .unprepare. Move it to .disable and do similar for prepare, where we move the display on to the .enable. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-5-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Handle all regulatorsDavid Heidelberg
Recently we documented, there is more than vddio regulator, adapt the driver to work with VCI and POC regulator. Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-4-6cd55471e84e@ixit.cz
2025-11-19drm/panel: sofef00: Clean up panel description after s6e3fc2x01 removalDavid Heidelberg
Remove leftover from s6e3fc2x01 support drop and clarify supported panel. The Samsung SOFEF00 DDIC is used in multiple phones, so describe it properly and generalize. Fixes: e1eb7293ab41 ("drm/panel: samsung-sofef00: Drop s6e3fc2x01 support") Signed-off-by: David Heidelberg <david@ixit.cz> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251119-sofef00-rebuild-v3-3-6cd55471e84e@ixit.cz
2025-11-19drm/panel: ilitek-ili9881d: Add support for Wanchanglong W552946AAA panelChaoyi Chen
W552946AAA is a panel by Wanchanglong. This panel utilizes the Ilitek ILI9881D controller. W552946AAA is similar to W552946ABA, but the W552946AAA only uses 2 lanes. Tested on rk3506g-evb1-v10. Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251106020632.92-6-kernel@airkyi.com
2025-11-19drm/panel: ronbo-rb070d30: fix warning with gpio controllers that sleepJosua Mayer
The ronbo-rb070d30 controles the various gpios for reset, standby, vertical and horizontal flip using the non-sleeping gpiod_set_value() function. Switch to using gpiod_set_value_cansleep() when controlling reset_gpio to support GPIO providers that may sleep, such as I2C GPIO expanders. This fixes noisy complaints in kernel log for gpio providers that do sleep. Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251117-imx8mp-hb-iiot-v3-5-bf1a4cf5fa8e@solid-run.com
2025-11-19drm/panel: jadard-jd9365da-h3: Use dev_err_probe() instead of ↵Abhishek Rajput
DRM_DEV_ERROR() during probing The DRM_DEV_ERROR() has been deprecated, and use dev_err_probe() can be better. The other reason is that dev_err_probe() help avoid unexpected repeated err logs during defered probing. Signed-off-by: Abhishek Rajput <abhiraj21put@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251117064702.222424-1-abhiraj21put@gmail.com
2025-11-19drm/panel: simple: Add Raystar RFF500F-AWH-DNN panel entryFabio Estevam
Add support for the Raystar RFF500F-AWH-DNN 5.0" TFT 840x480 LVDS panel. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251115025827.3113790-3-festevam@gmail.com
2025-11-19gpu/drm: panel: simple-panel: add Samsung LTL106AL01 LVDS panel supportSvyatoslav Ryhel
Samsung LTL106AL01 is a 10.6" FWXGA (1366x768) simple LVDS panel found in Microsoft Surface RT tablet. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251110091440.5251-6-clamor95@gmail.com
2025-11-19gpu/drm: panel: add support for LG LD070WX3-SL01 MIPI DSI panelSvyatoslav Ryhel
The LD070WX3 is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally Black mode. This TFT-LCD has 7.0 inches diagonally measured active display area with WXGA resolution (800 by 1280 pixel array). LG LD070WX3-SL01 MIPI DSI panel was treated as simple DSI panel when it is actually not and requires proper setup for correct work. Simple panel work relied on preliminary configuration done by bootloader. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251110091440.5251-3-clamor95@gmail.com
2025-11-19drm/xe/vm: Use for_each_tlb_inval() to calculate invalidation fencesMatt Roper
ops_execute() calculates the size of a fence array based on XE_MAX_GT_PER_TILE, while the code that actually fills in the fence array uses a for_each_tlb_inval() iterator. This works out okay today since both approaches come up with the same number of invalidation fences (2: primary GT invalidation + media GT invalidation), but could be problematic in the future if there isn't a 1:1 relationship between TLBs needing invalidation and potential GTs on the tile. Adjust the allocation code to use the same for_each_tlb_inval() counting logic as the code that fills the array to future-proof the code. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20251118202604.3715782-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-19Merge drm/drm-fixes into drm-misc-fixesThomas Zimmermann
Backmerging to get fixes from v6.18-rc6. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2025-11-19drm/i915/cx0: Enable dpll framework for MTL+Mika Kahola
MTL+ platforms are supported by dpll framework remove a separate check for hw comparison and rely solely on dpll framework hw comparison. Finally, all required hooks are now in place so initialize PLL manager for MTL+ platforms and remove the redirections to the legacy code paths from the following interfaces: * intel_encoder::clock_enable/disable() * intel_encoder::get_config() * intel_dpll_funcs::get_hw_state() * intel_ddi_update_active_dpll() * pipe_config_pll_mismatch() v2: Rebase on !HAS_LT_PHY check in intel_ddi_update_active_dpll() v3: Rebase on !display->dpll.mgr check in intel_ddi_update_active_dpll() Add check for NVL as the platform is not part of pll framework (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251118132859.2584452-1-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ Thunderbolt PLL hooksImre Deak
Add the PLL hooks for the TBT PLL on MTL+. These are simple stubs similarly to the TBT PLL on earlier platforms, since this PLL is always on from the display POV - so no PLL enable/disable programming is required as opposed to the non-TBT PLLs - and the clocks for different link rates are enabled/disabled at a different level, via the intel_encoder::enable_clock()/disable_clock() interface. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-32-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLsMika Kahola
For DDI initialization get encoder configuration for C10 and C20 chips. v2: Get configuration either for a C10 or on the PTL port B eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this case as "non_tc_phy" instead of "c10phy". Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-31-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola
To enable pll clock on DDI move part of the pll enabling sequence into a ddi clock enabling function. Simililarly, do the same for pll disabling sequence. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-30-mika.kahola@intel.com
2025-11-19drm/i915/cx0: PLL verify debug state printImre Deak
Print out hw and sw pll states for better debugging support. Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-29-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .crtc_get_dpll hookMika Kahola
Add .crtc_get_dpll function pointer to support MTL+ platforms. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-28-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .get_freq hookMika Kahola
Add .get_freq hook to support dpll framework for MTL+ platforms. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-27-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola
Add .get_hw_state hook to MTL+ platforms for dpll framework. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-26-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add .compare_hw_state hookMika Kahola
Add .compare_hw_state function pointer for MTL+ platforms to support dpll framework. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-25-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola
Add .dump_hw_state function pointer for MTL+ platforms to support dpll framework. While at it, switch to use drm_printer structure to print hw state information. v2: Keep debug messages on one line if they not necessarily needed to split into two or more lines (Suraj) Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-24-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hookMika Kahola
Add .update_dpll_ref_clks function pointer to MTL+ platforms to support dpll framework. Reuse ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-23-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .update_active_dpll hookMika Kahola
Add .update_active_dpll function pointer to support dpll framework. Reuse ICL function pointer. v2: Add check for !HAS_LT_PHY (Suraj) v3: Remove the incorrect !HAS_LT_PHY condition and check for existing dpll_mgr Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1 Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251118132830.2584422-1-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .put_dplls hookMika Kahola
Add .put_dplls function pointer to support MTL+ platforms on dpll framework. Reuse ICL function pointer. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-21-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Add MTL+ .get_dplls hookMika Kahola
Add .get_dplls function pointer for MTL+ platforms to support dpll framework. Reuse the ICL function pointer. v2: Getting configuration either for a C10 or on the PTL port B eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this case as "non_tc_phy" instead of "c10phy". v3: Fix comment to "eDP over TypeC" (Suraj) Fix pll id as separate variable (Suraj) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-20-mika.kahola@intel.com
2025-11-19drm/i915/cx0: Compute plls for MTL+ platformMika Kahola
To bring MTL+ platform aligned call and calculate PLL state from dpll framework. v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll(). The state is computed either for a C10 or on the PTL port B eDP over TypeC PHY case for a C20 PHY PLL. Hence refer to this case as "non_tc_phy" instead of "c10phy". Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for symmetry with mtl_compute_non_tc_phy_dpll(). v3: Reword commit message (Suraj) Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20251117104602.2363671-19-mika.kahola@intel.com
2025-11-19drm/xe: Switch to use %ptSpAndy Shevchenko
Use %ptSp instead of open coded variants to print content of struct timespec64 in human readable format. Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20251113150217.3030010-9-andriy.shevchenko@linux.intel.com Signed-off-by: Petr Mladek <pmladek@suse.com>
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-16 18:37:18 +0000