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path: root/drivers/gpu
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2025-12-10drm/amdgpu: Remove redundant check for async_gfx_ringHawking Zhang
Remove the redundant check for async_gfx_ring, as it is not required for gfx v12_1 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: disable graphics doorbell range for gfx v12_1Likun Gao
Disable doorbell range for graphics engine on gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: enable unmap doorbell handle for gfx v12_1Likun Gao
Enable unmapped doorbell handling for gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: revision doorbel range for gfx v12_1Likun Gao
Revision doorbell range on muti-XCC mode for gfx v12_1. Clean up doorbell range set for graphics engine. V2: Remove doorbell range set from gfx_v12_1_xcc_kiq_init_register. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdkfd: disable shader message vgpr deallocation on gc 12.1Jonathan Kim
Shader messages to deallocate VGPRs prior to shader end can prevent the trap handler from saving context, making debugging and core dumps unreliable. VGPR deallocations for performance gain is negligible. GC 12.1 will NOP shader VGPR deallocation messages via HW settings on driver boot. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Acked-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Remove redundant pmfw backdoor loadingHawking Zhang
PMFW is integrated into ifwi for gfx 12_1 adapter, making PMFW backdoor loading unnecessary. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amd: Fix unbind/rebind for VCN 4.0.5Mario Limonciello (AMD)
Unbinding amdgpu has no problems, but binding it again leads to an error of sysfs file already existing. This is because it wasn't actually cleaned up on unbind. Add the missing cleanup step. Fixes: 547aad32edac ("drm/amdgpu: add VCN4 ip block support") Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu/acpi: Reduce amdgpu_acpi_detect stack usageSrinivasan Shanmugam
amdgpu_acpi_detect() calls some helper functions it calls have large local structures. When the compiler inlines these helpers, their local data adds to the amdgpu_acpi_detect() stack frame. Mark the helpers with noinline_for_stack: - amdgpu_atif_verify_interface() - amdgpu_atif_get_notification_params() - amdgpu_atif_query_backlight_caps() - amdgpu_atcs_verify_interface() - amdgpu_acpi_enumerate_xcc() This keeps the large temporary objects inside the helper’s own stack frame instead of being inlined into the caller, preventing the caller from growing beyond the stack limit. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:1403:6: warning: stack frame size (1688) exceeds limit (1024) in 'amdgpu_acpi_detect' [-Wframe-larger-than] Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/xe/guc: Recommend GuC v70.54.0 for BMG, PTLJulia Filipchuk
UAPI compatibility version 1.27.0 Update recommended GuC version for BMG, PTL. Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20251125014134.2075988-15-julia.filipchuk@intel.com
2025-12-10drm/xe/guc: Recommend GuC v70.53.0 for MTL, DG2, LNLJulia Filipchuk
UAPI compatibility version 1.26.0 Update recommended GuC version for MTL, DG2, LNL. Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20251125014134.2075988-14-julia.filipchuk@intel.com
2025-12-10drm/i915: Fix BO alloc flagsLoïc Molinari
I915_BO_ALLOC_NOTHP must be added to the I915_BO_ALLOC_FLAGS mask in order to pass GEM_BUG_ON() valid flags checks. v2: - Add Tvrtko's A-b Reported-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Closes: https://lore.kernel.org/intel-gfx/d73adfa8-d61b-46b3-9385-dde53d8db8ad@intel.com/ Fixes: a8a9a590221c ("drm/i915: Use huge tmpfs mountpoint helpers") Suggested-by: Tvrtko Ursulin <tursulin@ursulin.net> Signed-off-by: Loïc Molinari <loic.molinari@collabora.com> Acked-by: Tvrtko Ursulin <tursulin@ursulin.net> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patch.msgid.link/20251210143617.712808-1-loic.molinari@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-10drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug messageImre Deak
On C10 PHY PLLs the SSC is enabled by programming the XELPDP_PORT_CLOCK_CTL / XELPDP_SSC_ENABLE_PLLB flag and the PHY_C10_VDR_PLL 4..8 registers: - If SSC is enabled XELPDP_SSC_ENABLE_PLLB is set and the PHY_C10_VDR_PLL registers are programmed to non-zero values. - If SSC is disabled XELPDP_SSC_ENABLE_PLLB is cleared and the PHY_C10_VDR_PLL registers are programmed to zeroed-out values. The driver's state checker verifies if the above settings are consistent, i.e. if XELPDP_SSC_ENABLE_PLLB being set corresponds to the PHY_C10_VDR_PLL registers being zeroed-out or not. On WCL the BIOS programs non-zero values to the PHY_C10_VDR_PLL 4..8 registers, but does not set the XELPDP_SSC_ENABLE_PLLB flag. This will trigger the following PLL state check warning during driver loading: <4>[ 44.457809] xe 0000:00:02.0: [drm] PHY B: SSC enabled state (no), doesn't match PLL configuration (SSC-enabled) <4>[ 44.457833] WARNING: CPU: 4 PID: 298 at drivers/gpu/drm/i915/display/intel_cx0_phy.c:2281 intel_cx0pll_readout_hw_state+0x221/0x620 [xe] It's not clear whether the HW uses the PHY_C10_VDR_PLL 4..8 register values if the XELPDP_SSC_ENABLE_PLLB flag is cleared, or just ignores them in this case. Since the driver always programs the register values according to the above, it still makes sense to verify that the programming happened correctly. To avoid the state check WARN during driver loading due to the way BIOS programs the registers, convert the WARN to a debug message. While at it clarify the debug message. v2: Clarify the debug message. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251209153407.1791839-1-imre.deak@intel.com
2025-12-10drm/gem: Fix builds with CONFIG_MMU=nBoris Brezillon
drm_gem_get_unmapped_area() relies on mm_get_unmapped_area() which is only available if CONFIG_MMU=y. Fixes: 99bda20d6d4c ("drm/gem: Introduce drm_gem_get_unmapped_area() fop") Cc: Loïc Molinari <loic.molinari@collabora.com> Reviewed-by: Loïc Molinari <loic.molinari@collabora.com> Link: https://patch.msgid.link/20251209171151.2449120-1-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-10drm/i915/psr: Allow async flip when Selective Fetch enabledJouni Högander
Now as Selective Fetch is performing full frame update on async flip and vblank evasion is done as needed we can allow async flip even when Selective Fetch is enabled. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251204070718.1090778-4-jouni.hogander@intel.com
2025-12-10drm/i915/psr: Perform full frame update on async flipJouni Högander
According to bspec selective fetch is not supported with async flips and instructing full frame update on async flip. v4: - check crtc_state->async_flip_planes in psr2_sel_fetch_pipe_state_supported v3: - rebase - fix old_crtc_state->pipe_srcsz_early_tpt - fix using intel_atomic_get_new_crtc_state v2: - check also crtc_state->async_flip_planes in psr2_sel_fetch_plane_state_supported Bspec: 55229 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251204070718.1090778-3-jouni.hogander@intel.com
2025-12-10drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSRJouni Högander
Currently plane id bit is set in crtc_state->async_flip_planes only when async flip toggle workaround is needed. We want to utilize crtc_state->async_flip_planes further in Selective Fetch calculation. v2: - rework if-else if to if-if - added comment updated Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251204070718.1090778-2-jouni.hogander@intel.com
2025-12-10drm/{i915, xe}/stolen: make insert_node, area_address, area_size optionalJani Nikula
Since the stolen memory hooks are function pointers, make some of them optional instead of having to define them for xe. insert_node, area_address, and area_size are only needed on platforms not supported by xe. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/0dbb460e8bd1df29df98862d08fcdfda03912673.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/{i915, xe}/stolen: move stolen memory handling to display parent interfaceJani Nikula
Call the stolen memory interface through the display parent interface. This makes xe compat gem/i915_gem_stolen.h redundant, and it can be removed. v2: Rebase, convert one more call that appeared Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/350c82c49fe40f6319d14d309180e2e2752145ac.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/xe/stolen: unify interface with i915Jani Nikula
Have i915_gem_stolen_node_offset() return u64, and pass const pointer to them. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/e1ae0c5d3cc6f59d6e4f4ce810a6e9b3870109f8.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/i915/fbc: let to_intel_display() do its generic magicJani Nikula
to_intel_display() generics can handle struct intel_plane_state, struct intel_atomic_state, and struct intel_crtc just fine. Pass them directly. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Link: https://patch.msgid.link/14d0979eea358fb3713640eae74a7a8801cd8eec.1764930576.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/Kconfig: sort driver Kconfig source listJani Nikula
Sort the driver Kconfig source list, and remove the superfluous blank lines in between. Reviewed-by: Louis Chauvet <louis.chauvet@bootlin.com> Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/4fa11ab0b938d5c726b6ad78d28c7527b830f696.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/Kconfig: move generic Kconfig options above driversJani Nikula
Keep non-driver options together, above drivers. DRM_PANEL_ORIENTATION_QUIRKS remains alone at the end because it's outside of the whole "if DRM" block. Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/a0f9e1a31a2190f535f2c2f94af6e22030db199f.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/vgem: move Kconfig under driver directoryJani Nikula
Almost all DRM driver Kconfig options are in dedicated Kconfig files under driver directories. Follow suit in vgem. Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/51935bfb299e8c64beae5a654d908231e2ec9c7f.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/hyperv: move Kconfig under driver directoryJani Nikula
Almost all DRM driver Kconfig options are in dedicated Kconfig files under driver directories. Follow suit in hyperv. Cc: Deepak Rawat <drawat.floss@gmail.com> Reviewed-by: Deepak Rawat <drawat.floss@gmail.com> Reviewed-by: Maarten Lankhorst <dev@lankhorst.se> Link: https://patch.msgid.link/4923196ab968bfdbcc2d7572d9be9886c32c06c9.1762251845.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-10drm/mgag200: Fix big-endian supportRené Rebe
Unlike the original, deleted Matrox mga driver, the new mgag200 driver has the XRGB frame-buffer byte swapped on big-endian "RISC" systems. Fix by enabling byte swapping "PowerPC" OPMODE for any __BIG_ENDIAN config. Fixes: 414c45310625 ("mgag200: initial g200se driver (v2)") Signed-off-by: René Rebe <rene@exactco.de> Cc: stable@kernel.org Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251208.141827.965103015954471168.rene@exactco.de
2025-12-09drm/xe/xe_survivability: Add support for survivability mode v2Riana Tauro
v2 survivability breadcrumbs introduces a new mode called SPI Flash Descriptor Override mode (FDO). This is enabled by PCODE when MEI itself fails and firmware cannot be updated via MEI using igsc. This mode provides the ability to update the firmware directly via SPI driver. Xe KMD initializes the nvm aux driver if FDO mode is enabled. Userspace should check FDO mode entry in survivability info sysfs before using the SPI driver to update firmware. /sys/bus/pci/devices/<device>/survivability_info/fdo_mode v2 also supports survivability mode for critical boot errors. Signed-off-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20251208084539.3652902-6-riana.tauro@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-12-09drm/xe/xe_survivability: Redesign survivability modeRiana Tauro
Redesign survivability mode to have only one value per file. 1) Retain the survivability_mode sysfs to indicate the type cat /sys/bus/pci/devices/0000\:03\:00.0/survivability_mode (Boot / Runtime) 2) Add survivability_info directory to expose boot breadcrumbs. Entries in survivability mode sysfs are only visible when boot breadcrumb registers are populated. /sys/bus/pci/devices/0000:03:00.0/survivability_info ├── aux_info0 ├── aux_info1 ├── aux_info2 ├── aux_info3 ├── aux_info4 ├── capability_info ├── postcode_trace └── postcode_trace_overflow Capability Info: Provides data about boot status and has bits that indicate the support for the other breadcrumbs Postcode Trace / Postcode Trace Overflow : Each postcode is represented as an 8-bit value and represents a boot failure event. When a new failure event is logged by Pcode the existing postcodes are shifted left. These entries provide a history of 8 postcodes. Auxiliary Info: Some failures have additional debug information. Signed-off-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20251208084539.3652902-5-riana.tauro@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-12-09drm/xe/vf: Stop waiting for ring space on VF post migration recoveryTomasz Lis
If wait for ring space started just before migration, it can delay the recovery process, by waiting without bailout path for up to 2 seconds. Two second wait for recovery is not acceptable, and if the ring was completely filled even without the migration temporarily stopping execution, then such a wait will result in up to a thousand new jobs (assuming constant flow) being added while the wait is happening. While this will not cause data corruption, it will lead to warning messages getting logged due to reset being scheduled on a GT under recovery. Also several seconds of unresponsiveness, as the backlog of jobs gets progressively executed. Add a bailout condition, to make sure the recovery starts without much delay. The recovery is expected to finish in about 100 ms when under moderate stress, so the condition verification period needs to be below that - settling at 64 ms. The theoretical max time which the recovery can take depends on how many requests can be emitted to engine rings and be pending execution. While stress testing, it was possible to reach 10k pending requests on rings when a platform with two GTs was used. This resulted in max recovery time of 5 seconds. But in real life situations, it is very unlikely that the amount of pending requests will ever exceed 100, and for that the recovery time will be around 50 ms - well within our claimed limit of 100ms. Fixes: a4dae94aad6a ("drm/xe/vf: Wakeup in GuC backend on VF post migration recovery") Signed-off-by: Tomasz Lis <tomasz.lis@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251204200820.2206168-1-tomasz.lis@intel.com
2025-12-09drm/xe/xe3p_xpc: Enable Indirect Ring State for xe3p_xpcNiranjana Vishwanathapura
The xe3p_xpc platform supports Indirect Ring State and it is required for the upcoming multi-queue feature. Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251204063451.1180387-2-niranjana.vishwanathapura@intel.com
2025-12-09drm/i915: Fix format string truncation warningArd Biesheuvel
GCC notices that the 16-byte uabi_name field could theoretically be too small for the formatted string if the instance number exceeds 100. So grow the field to 20 bytes. drivers/gpu/drm/i915/intel_memory_region.c: In function ‘intel_memory_region_create’: drivers/gpu/drm/i915/intel_memory_region.c:273:61: error: ‘%u’ directive output may be truncated writing between 1 and 5 bytes into a region of size between 3 and 11 [-Werror=format-truncation=] 273 | snprintf(mem->uabi_name, sizeof(mem->uabi_name), "%s%u", | ^~ drivers/gpu/drm/i915/intel_memory_region.c:273:58: note: directive argument in the range [0, 65535] 273 | snprintf(mem->uabi_name, sizeof(mem->uabi_name), "%s%u", | ^~~~~~ drivers/gpu/drm/i915/intel_memory_region.c:273:9: note: ‘snprintf’ output between 7 and 19 bytes into a destination of size 16 273 | snprintf(mem->uabi_name, sizeof(mem->uabi_name), "%s%u", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 274 | intel_memory_type_str(type), instance); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: 3b38d3515753 ("drm/i915: Add stable memory region names") Cc: <stable@vger.kernel.org> # v6.8+ Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net> Link: https://lore.kernel.org/r/20251205113500.684286-2-ardb@kernel.org (cherry picked from commit 18476087f1a18dc279d200d934ad94fba1fb51d5) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-09drm/i915/fbdev: Hold runtime PM ref during fbdev BO creationDibin Moolakadan Subrahmanian
During fbdev probe, the xe driver allocates and pins a framebuffer BO (via xe_bo_create_pin_map_novm() → xe_ggtt_insert_bo()). Without a runtime PM reference, xe_pm_runtime_get_noresume() warns about missing outer PM protection as below: xe 0000:03:00.0: [drm] Missing outer runtime PM protection Acquire a runtime PM reference before framebuffer allocation to ensure xe_ggtt_insert_bo() executes under active runtime PM context. Changes in v2: - Update commit message to add Fixes tag (Jani Nikula) Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6350 Fixes: 44e694958b95 ("drm/xe/display: Implement display support") Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251111135403.3415947-1-dibin.moolakadan.subrahmanian@intel.com (cherry picked from commit 37fc7b7b3ab0e3bb900657199cd3770a4fda03fb) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-09drm/i915/crtc: move crtc initialization loop to intel_crtc.cJani Nikula
intel_display_driver_probe_nogem() is too high of an abstraction level to be looping and initializing individual CRTCs. Move this to intel_crtc.c and repurpose intel_crtc_init() to initialize all CRTCs. Make the original a static __intel_crtc_init() for initializing a single CRTC. Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://patch.msgid.link/20251204143235.3138973-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-09drm/panfrost: Bump the driver version to 1.6Faith Ekstrand
Bump the driver version to reflect the new cached-CPU mapping capability. v2: - Quickly describe what the new version exposes in the commit message v3: - Add Steve's R-b v4: - No changes v5: - No changes v6: - No changes v7: - No changes v8: - No changes Signed-off-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-14-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panfrost: Add flag to map GEM object Write-Back CacheableFaith Ekstrand
Will be used by the UMD to optimize CPU accesses to buffers that are frequently read by the CPU, or on which the access pattern makes non-cacheable mappings inefficient. Mapping buffers CPU-cached implies taking care of the CPU cache maintenance in the UMD, unless the GPU is IO coherent. v2: - Add more to the commit message v3: - No changes v4: - Fix the map_wc test in panfrost_ioctl_query_bo_info() v5: - Drop Steve's R-b (enough has changed to justify a new review) v6: - Collect R-b v7: - No changes v8: - Fix double drm_gem_object_funcs::export assignment Signed-off-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-13-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panfrost: Add an ioctl to query BO flagsBoris Brezillon
This is useful when importing BOs, so we can know about cacheability and flush the caches when needed. v2: - New commit v3: - Add Steve's R-b v4: - No changes v5: - No changes v6: - No changes v7: - No changes v8: - No changes Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-12-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panfrost: Add a PANFROST_SYNC_BO ioctlFaith Ekstrand
This will be used by the UMD to synchronize CPU-cached mappings when the UMD can't do it directly (no usermode cache maintenance instruction on Arm32). v2: - Add more to the commit message - Change the flags to better match the drm_gem_shmem_sync semantics v3: - Add Steve's R-b v4: - No changes v5: - Drop Steve's R-b (semantics changes requiring a new review) v6: - Bail out early in panfrost_ioctl_sync_bo() if op_count is zero v7: - Hand-roll our own bo_sync() helper v8: - Collect R-b Signed-off-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-11-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panfrost: Expose the selected coherency protocol to the UMDBoris Brezillon
Will be needed if we want to skip CPU cache maintenance operations when the GPU can snoop CPU caches. v2: - New commit v3: - Fix the coherency values (enum instead of bitmask) v4: - Fix init/test on coherency_features v5: - No changes v6: - Collect R-b v7: - No changes v8: - No changes Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-10-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panfrost: Provide a custom dma_buf implementationBoris Brezillon
Before we introduce cached CPU mappings, we want a dma_buf implementation satisfying synchronization requests around CPU accesses coming from a dma_buf exported by our driver. Let's provide our own implementation relying on the default gem_shmem_prime helpers designed for that purpose. v5: - New patch v6: - Collect R-b v7: - Hand-roll our own dma_buf boilerplate v8: - No changes Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-9-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panthor: Bump the driver version to 1.7Faith Ekstrand
Bump the driver version to reflect the new cached-CPU mapping capability. v2: - Quickly describe what the new version exposes in the commit message v3: - Add Steve's R-b v4: - No changes v5: - No changes v6: - No changes v7: - No changes v8: - Bump to 1.7 (1.6 was picked in the meantime) Signed-off-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-8-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panthor: Add flag to map GEM object Write-Back CacheableLoïc Molinari
Will be used by the UMD to optimize CPU accesses to buffers that are frequently read by the CPU, or on which the access pattern makes non-cacheable mappings inefficient. Mapping buffers CPU-cached implies taking care of the CPU cache maintenance in the UMD, unless the GPU is IO coherent. v2: - Add more to the commit message - Tweak the doc - Make sure we sync the section of the BO pointing to the CS syncobj before we read its seqno v3: - Fix formatting/spelling issues v4: - Add Steve's R-b v5: - Drop Steve's R-b (changes in the ioctl semantics requiring new review) v6: - Fix the uAPI doc - Fix inverted logic in some comment v7: - No changes v8: - Collect R-b Signed-off-by: Loïc Molinari <loic.molinari@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-7-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panthor: Add an ioctl to query BO flagsBoris Brezillon
This is useful when importing BOs, so we can know about cacheability and flush the caches when needed. We can also know when the buffer comes from a different subsystem and take proper actions (avoid CPU mappings, or do kernel-based syncs instead of userland cache flushes). v2: - New commit v3: - Add Steve's R-b v4: - No changes v5: - No changes v6: - No changes v7: - No changes v8: - No changes Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-6-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panthor: Add a PANTHOR_BO_SYNC ioctlBoris Brezillon
This will be used by the UMD to synchronize CPU-cached mappings when the UMD can't do it directly (no usermode cache maintenance instruction on Arm32). v2: - Change the flags so they better match the drm_gem_shmem_sync() semantics v3: - Add Steve's R-b v4: - No changes v5: - Drop Steve's R-b (the semantics changes call for a new review) v6: - Drop ret initialization in panthor_ioctl_bo_sync() - Bail out early in panthor_ioctl_bo_sync() if ops.count is zero - Drop unused PANTHOR_BO_SYNC_OP_FLAGS definition v7: - Hand-roll the sync logic (was previously provided by gem_shmem) v8: - Collect R-b Signed-off-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-5-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panthor: Expose the selected coherency protocol to the UMDBoris Brezillon
If we want to be able to skip CPU cache maintenance operations on CPU-cached mappings, the UMD needs to know the kind of coherency in place. Add a field to drm_panthor_gpu_info to do that. We can re-use a padding field for that since this object is write-only from the KMD perspective, and the UMD should just ignore it. v2: - New commit v3: - Make coherency protocol a real enum, not a bitmask - Add BUILD_BUG_ON()s to make sure the values in panthor_regs.h and those exposed through the uAPI match v4: - Add Steve's R-b v5: - No changes v6: - No changes v7: - Fix kernel doc v8: - No changes Reviewed-by: Steven Price <steven.price@arm.com> Reviewed-by: Karunika Choo <karunika.choo@arm.com> Link: https://patch.msgid.link/20251208100841.730527-4-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panthor: Fix panthor_gpu_coherency_set()Boris Brezillon
GPU_COHERENCY_PROTOCOL takes one of GPU_COHERENCY_xx not BIT(GPU_COHERENCY_xx). v3: - New commit v4: - Add Steve's R-b v5: - No changes v6: - No changes v7: - No changes v8: - No changes Cc: Akash Goel <akash.goel@arm.com> Fixes: dd7db8d911a1 ("drm/panthor: Explicitly set the coherency mode") Reported-by: Steven Price <steven.price@arm.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-3-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-09drm/panthor: Provide a custom dma_buf implementationBoris Brezillon
Before we introduce cached CPU mappings, we want a dma_buf implementation satisfying synchronization requests around CPU accesses coming from a dma_buf exported by our driver. Let's provide our own implementation relying on the default gem_shmem_prime helpers designed for that purpose. v5: - New patch v6: - Collect R-b v7: - Hand-roll the dma_buf sync/import logic (was previously done by generic prime/shmem helpers) v8: - No changes Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251208100841.730527-2-boris.brezillon@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-12-08drm/amd/display: Improve HDMI info retrievalIvan Lipski
[WHY & HOW] Make a dedicated function to read HDMI-related monitor info, including monitor's SCDC support. Fixes: 3471b9a31ce3 ("drm/amd/display: Rework HDMI data channel reads") Suggested-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit c78e31bcf586f1c910a2636650840f5ce1cb1c63)
2025-12-08drm/panel-edp: Add AUO B140QAX01.H panelVal Packett
A 14-inch 2560x1600 60Hz matte touch panel, found on a Dell Latitude 7455 laptop (second-source with BOE NE14QDM), according to online sources it's also found on the Latitude 7440 and some ASUS models. Raw EDID dump: 00 ff ff ff ff ff ff 00 06 af a4 0b 00 00 00 00 00 20 01 04 a5 1e 13 78 03 ad f5 a8 54 47 9c 24 0e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 f0 68 00 a0 a0 40 2e 60 30 20 35 00 2d bc 10 00 00 1a f3 53 00 a0 a0 40 2e 60 30 20 35 00 2d bc 10 00 00 1a 00 00 00 fe 00 36 39 52 31 57 80 42 31 34 30 51 41 58 00 00 00 00 00 02 41 21 a8 00 01 00 00 1a 41 0a 20 20 00 a1 Don't have datasheet access, but the same timing as for other panels from the same manufacturer works fine. Signed-off-by: Val Packett <val@packett.cool> [dianders: Moved to the right location in the table] Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20251206173739.2222940-1-val@packett.cool
2025-12-08drm/tilcdc: Fix removal actions in case of failed probeKory Maincent (TI.com)
The drm_kms_helper_poll_fini() and drm_atomic_helper_shutdown() helpers should only be called when the device has been successfully registered. Currently, these functions are called unconditionally in tilcdc_fini(), which causes warnings during probe deferral scenarios. [ 7.972317] WARNING: CPU: 0 PID: 23 at drivers/gpu/drm/drm_atomic_state_helper.c:175 drm_atomic_helper_crtc_duplicate_state+0x60/0x68 ... [ 8.005820] drm_atomic_helper_crtc_duplicate_state from drm_atomic_get_crtc_state+0x68/0x108 [ 8.005858] drm_atomic_get_crtc_state from drm_atomic_helper_disable_all+0x90/0x1c8 [ 8.005885] drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x90/0x144 [ 8.005911] drm_atomic_helper_shutdown from tilcdc_fini+0x68/0xf8 [tilcdc] [ 8.005957] tilcdc_fini [tilcdc] from tilcdc_pdev_probe+0xb0/0x6d4 [tilcdc] Fix this by rewriting the failed probe cleanup path using the standard goto error handling pattern, which ensures that cleanup functions are only called on successfully initialized resources. Additionally, remove the now-unnecessary is_registered flag. Cc: stable@vger.kernel.org Fixes: 3c4babae3c4a ("drm: Call drm_atomic_helper_shutdown() at shutdown/remove time for misc drivers") Signed-off-by: Kory Maincent (TI.com) <kory.maincent@bootlin.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20251125090546.137193-1-kory.maincent@bootlin.com
2025-12-08drm/amdkfd: bump minimum vgpr size for gfx1151Jonathan Kim
GFX1151 has 1.5x the number of available physical VGPRs per SIMD. Bump total memory availability for acquire checks on queue creation. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit b42f3bf9536c9b710fd1d4deb7d1b0dc819dc72d) Cc: stable@vger.kernel.org
2025-12-08drm/amd/display: shrink struct membersRosen Penev
On a 32-bit ARM system, the audio_decoder struct ends up being too large for dp_retrain_link_dp_test. link_dp_cts.c:157:1: error: the frame size of 1328 bytes is larger than 1280 bytes [-Werror=frame-larger-than=] This is mitigated by shrinking the members of the struct and avoids having to deal with dynamic allocation. feed_back_divider is assigned but otherwise unused. Remove both. pixel_repetition looks like it should be a bool since it's only ever assigned to 1. But there are checks for 2 and 4. Reduce to uint8_t. Remove ss_percentage_divider. Unused. Shrink refresh_rate as it gets assigned to at most a 3 digit integer value. Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 3849efdc7888d537f09c3dcfaea4b3cd377a102e)
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-13 06:09:21 +0000