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2026-01-05drm/amdgpu: only check critical address when it is not reservedGangliang Xie
when an address is reserved already, no need to check if it is in critical or not, to save time Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Fix query for VPE block_type and ip_countAlan Liu
[Why] Query for VPE block_type and ip_count is missing. [How] Add VPE case in ip_block_type and hw_ip_count query. Reviewed-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/ras: Replace NPS flags in ras moduleJinzhou Su
Replace AMDGPU_NPS8_PARTITION_MODE with UMC_MEMORY_PARTITION_MODE_NPS8 to pass sriov compilation. Signed-off-by: Jinzhou Su <jinzhou.su@amd.com> Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Don't repeat DAC load detectionTimur Kristóf
The analog link detection code path had already performed the DAC load detection by the time the EDID read is attempted. So there is no need to repeat the DAC load detection, we can know that no display is connected if no EDID is read. Fixes: ac1bb4952267 ("drm/amd/display: Use DAC load detection on analog connectors (v2)") Suggested-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Add missing encoder setup to DACnEncoderControlTimur Kristóf
Apparently the DAC encoder needs to be set up before use. The BIOS parser in DC did not support this so I assumed it was not necessary, but the DAC doesn't work without it on some GPUs. Fixes: 69b29b894660 ("drm/amd/display: Hook up DAC to bios_parser_encoder_control") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Correct color depth for SelectCRTC_SourceTimur Kristóf
Pass the correct enum values as expected by the VBIOS. Previously the actual bit depth integer value was passed, which was a mistake. Fixes: 7fb4f254c8eb ("drm/amd/display: Add SelectCRTC_Source to BIOS parser") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Pass proper DAC encoder ID to VBIOSTimur Kristóf
Similarly to the analog_engine field, add a new analog_id field which contains the encoder ID of the analog encoder that corresponds to the link encoder. Previously, the default encoder ID of the link encoder was used, which meant that we passed the wrong ID in case of DVI-I. Fixes: 5834c33fd3f6 ("drm/amd/display: Add concept of analog encoders (v2)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/gfx9: Implement KGQ ring resetAlex Deucher
GFX ring resets work differently on pre-GFX10 hardware since there is no MQD managed by the scheduler. For ring reset, you need issue the reset via CP_VMID_RESET via KIQ or MMIO and submit the following to the gfx ring to complete the reset: 1. EOP packet with EXEC bit set 2. WAIT_REG_MEM to wait for the fence 3. Clear CP_VMID_RESET to 0 4. EVENT_WRITE ENABLE_LEGACY_PIPELINE 5. EOP packet with EXEC bit set 6. WAIT_REG_MEM to wait for the fence Once those commands have completed the reset should be complete and the ring can accept new packets. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Tested-by: Jiqian Chen <Jiqian.Chen@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/gfx9: rework pipeline sync packet sequenceAlex Deucher
Replace WAIT_REG_MEM with EVENT_WRITE flushes for all shader types and ACQUIRE_MEM. That should accomplish the same thing and avoid having to wait on a fence preventing any issues with pipeline syncs during queue resets. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: avoid a warning in timedout job handlerAlex Deucher
Only set an error on the fence if the fence is not signalled. We can end up with a warning if the per queue reset path signals the fence and sets an error as part of the reset, but fails to recover. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/amdgpu: Fix SMU warning during isp suspend-resumePratap Nirujogi
ISP mfd child devices are using genpd and the system suspend-resume operations between genpd and amdgpu parent device which uses only runtime suspend-resume are not in sync. Linux power manager during suspend-resume resuming the genpd devices earlier than the amdgpu parent device. This is resulting in the below warning as SMU is in suspended state when genpd attempts to resume ISP. WARNING: CPU: 13 PID: 5435 at drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.c:398 smu_dpm_set_power_gate+0x36f/0x380 [amdgpu] To fix this warning isp suspend-resume is handled as part of amdgpu parent device suspend-resume instead of genpd sequence. Each ISP MFD child device is marked as dev_pm_syscore_device to skip genpd suspend-resume and use pm_runtime_force api's to suspend-resume the devices when callbacks from amdgpu are received. Co-developed-by: Gjorgji Rosikopulos <grosikop@amd.com> Signed-off-by: Gjorgji Rosikopulos <grosikop@amd.com> Signed-off-by: Bin Du <bin.du@amd.com> Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Promote DC to 3.2.364Taimur Hassan
This version brings along the following updates: - Add frame skip feature support flag. - Add sink EDID data null check. - Update function name to link_detect_connection_type_analog. - Fix mismatched unlock for DMUB HW lock in HWSS fast path. - Fix P010, NV12, YUY2 scale down by four times failure. - Fix and reenable UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL. - Consolidate dmub fb info to a single struct. - Add new fields to fams2 config. - Update timing source enums. - Add signal type check for dcn401 get_phyd32clk_src. - Fix dsc eDP issue. - Remove unnecessary divider update flag. - Update dc_connection_dac_load to dc_connection_analog_load. - Check NULL before calling dac_load_detection. - Replace log macro for analog display detection. Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Replace log macro for analog display detectionAlex Hung
link detection should use LINK_INFO() macro. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Check NULL before calling dac_load_detectionAlex Hung
dac_load_detection can be NULL in some scenario, so checking it before calling. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Update dc_connection_dac_load to dc_connection_analog_loadAlex Hung
Update to a more accurate name dc_connection_analog_load. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Remove unnecessary divider update flagCruise Hung
[Why] When transitioning from 640x480 at RBRx1 to HBR3x1, both output pixel mode and pixel rate divider should update. The needs_divider_update flag was only for 8b10b and 128b132b transition. [How] Remove needs_divider_update flag. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Fix dsc eDP issueCharlene Liu
[why] Need to add function hook check before use Reviewed-by: Mohit Bawa <mohit.bawa@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Add signal type check for dcn401 get_phyd32clk_srcDmytro Laktyushkin
Trying to access link enc on a dpia link will cause a crash otherwise Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Update timing source enumsClay King
Added missing enum for CEA VIC Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Add new fields to fams2 configDillon Varone
[WHY&HOW] Adds new fields to the fams2 configuration structure. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Consolidate dmub fb info to a single structDillon Varone
[WHY&HOW] Consolidate dmub fb info into a single structure to simplify translation between components. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Fix and reenable UPDATE_V3_FLOW_NEW_CONTEXT_MINIMALDominik Kaszewski
[Why] Reenable new split implementation, previously partially reverted due to issues with ODM on high-bandwidth displays 4k144Hz, resulting in a corrupted gray screen. Minimal flows require two separate commits, with extra intermediate commit to enable seamless transitions, each followed by a swap. Since new design requires commit to be run in execute and swap in cleanup stage, an attempt was made to reorder them from CSCS (Commit-Swap-Commit-Swap) to CCSS (Commit-Commit-Swap-Swap). Not only is this not viable, but was implemented incorrectly as CCS, one swap missing. [How] * Change UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW/CURRENT to execute and cleanup one commit, then run UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS, which closely matches old implementation where minimal flows fall back to seamless. * Fix uninitialized variable error. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Fix P010, NV12, YUY2 scale down by four times failureKaier Hsueg
[WHY] When performing 4:1 downscaling with subsampled formats, the SPL remainder distribution logic (+1) overrides the upper layer’s aligned width, resulting in odd segment widths and causing hang. The upper layer alignment ensures the width is sufficient and even, so SPL should not modify it further. [HOW] In dc_spl.c within calculate_mpc_slice_in_timing_active, add an extra condition: Skip the remainder distribution (+1) when use_recout_width_aligned is true.This change respects the upper layer’s alignment decision, prevents odd widths, and is a minimal, safe fix. Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Kaier Hsueh <Kaier.Hsueh@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Fix mismatched unlock for DMUB HW lock in HWSS fast pathNicholas Kazlauskas
[Why] The evaluation for whether we need to use the DMUB HW lock isn't the same as whether we need to unlock which results in a hang when the fast path is used for ASIC without FAMS support. [How] Store a flag that indicates whether we should use the lock and use that same flag to specify whether unlocking is needed. Reviewed-by: Swapnil Patel <swapnil.patel@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Update function name to link_detect_connection_type_analogAlex Hung
[WHAT] Update function "link_detect_analog" to a more accurate name "link_detect_connection_type_analog". Suggested-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: sink EDID data null checkRichard Chiang
[Why] When sink EDID data pointer is NULL, it will cause an unexpected error. [How] Check data pointer is not NULL first. Reviewed-by: Yihan Zhu <yihan.zhu@amd.com> Signed-off-by: Richard Chiang <Richard.Chiang@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Add frame skip feature support flagChunTao Tso
[WHY] The set_replay_frame_skip_number() function should not execute when the link does not support the Frame Skipping feature. [HOW] Add a new field `frame_skip_supported` to struct replay_config to indicate whether the link supports frame skipping. Check this flag at the beginning of set_replay_frame_skip_number() and return early if the feature is not supported. Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: ChunTao Tso <chuntao.tso@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/pm: force send pcie parmater on navi1xYang Wang
v1: the PMFW didn't initialize the PCIe DPM parameters and requires the KMD to actively provide these parameters. v2: clean & remove unused code logic (lijo) Fixes: 1a18607c07bb ("drm/amd/pm: override pcie dpm parameters only if it is necessary") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4671 Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: use dma_fence_get_status() for adapter resetAlex Deucher
We need to check if the fence was signaled without an error as the per queue resets may have signalled the fence while attempting to reset the queue. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05Documentation/amdgpu: Add UMA carveout detailsYo-Jung Leo Lin (AMD)
Add documentation for the uma/carveout_options and uma/carveout attributes in sysfs Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add UMA allocation interfaces to sysfsYo-Jung Leo Lin (AMD)
Add a uma/ directory containing two sysfs files as interfaces to inspect or change UMA carveout size. These files are: - uma/carveout_options: a read-only file listing all the available UMA allocation options and their index. - uma/carveout: a file that is both readable and writable. On read, it shows the index of the current setting. Writing a valid index into this file allows users to change the UMA carveout size to that option on the next boot. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add UMA allocation setting helpersYo-Jung Leo Lin (AMD)
On some platforms, UMA allocation size can be set using the ATCS methods. Add helper functions to interact with this functionality. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add helper to read UMA carveout infoYo-Jung Leo Lin (AMD)
Currently, the available UMA allocation configs in the integrated system information table have not been parsed. Add a helper function to retrieve and store these configs. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: parse UMA size-getting/setting bits in ATCS maskYo-Jung Leo Lin (AMD)
The capabilities of getting and setting VRAM carveout size are exposed in the ATCS mask. Parse and store these capabilities for future use. Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: always backup and reemit fencesAlex Deucher
If when we backup the ring contents for reemit before a ring reset, we skip jobs associated with the bad context, however, we need to make sure the fences are reemited as unprocessed submissions may depend on them. v2: clean up fence handling, make helpers static Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: don't reemit ring contents more than onceAlex Deucher
If we cancel a bad job and reemit the ring contents, and we get another timeout, cancel everything rather than reemitting. The wptr markers are only relevant for the original emit. If we reemit, the wptr markers are no longer correct. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add helpers to access cross-die registers smn addr for soc v1_0Le Ma
Encode die_id/socket_id for upper 32bits of soc v1_0 registers SMN address. v2: fix logical error caught by clang Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: RLC-G VF Register Access InterfaceBokun Zhang
- Implement Gfx v12.1 VFi interface under SRIOV - Redirect all RLCG interface access to new function after Gfx v12.1 v2: squash in register updates Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: set aid_mask for soc v1Likun Gao
Set aid_mask via xcc_mask. v2: squash in follow up change Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Enable support for PSP 15_0_0Pratik Vishwakarma
Add support for PSP v 15.0.0. Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add MP 15.0.0 headersAlex Deucher
Add headers for MP 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add queue reset support for jpeg 5.3Alex Deucher
Enable queue reset for JPEG 5.3. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/discovery: add vcn and jpeg ip blockSaleemkhan Jamadar
Add VCN and jpeg IPs v5_3_0 blocks. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/jpeg: Add jpeg 5.3.0 supportSaleemkhan Jamadar
Add the Jpeg IP v5_3_0 code base. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add VCN 5.3.0 headersAlex Deucher
Add headers for VCN 5.3.0. v2: Squash in updates (Alex) Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: reserve umf hole size at vram high end for gfx v12.1Le Ma
This region is reserved by firmware thus carve it out in driver. v2: set reserve size based on aid configuration. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Use explicit VCN instance 0 in SR-IOV initSrinivasan Shanmugam
vcn_v2_0_start_sriov() declares a local variable "i" initialized to zero and uses it only as the instance index in SOC15_REG_OFFSET(UVD, i, ...). The value is never changed and all other fields are taken from adev->vcn.inst[0], so this path only ever programs VCN instance 0. This triggered a Smatch: warn: iterator 'i' not incremented Replace the dummy iterator with an explicit instance index of 0 in SOC15_REG_OFFSET() calls. Fixes: dd26858a9cd8 ("drm/amdgpu: implement initialization part on VCN2.0 for SRIOV") Reported by: Dan Carpenter <dan.carpenter@linaro.org> Cc: darlington Opara <darlington.opara@amd.com> Cc: Jinage Zhao <jiange.zhao@amd.com> Cc: Monk Liu <Monk.Liu@amd.com> Cc: Emily Deng <Emily.Deng@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: enable CP interrupt for gfx v12_1 in frontdoor loading caseLe Ma
Enable cp interrupt for event detection since GFX CGCG and LS has been enabled by firmware. v2: enable CP INT by merely checking fw_load_type Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Apply VGPR bank state fixup on gfx12.1 trap exitJay Cornwall
- Identify co-issue of S_SET_VGPR_MSB and VALU with banked VGPR - Restore previous bank setting when exiting the trap v2: - Refine VOP3PX2 detection - Improve load pipelining - Fix a comment typo Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Cc: Joseph Greathouse <joseph.greathouse@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Fix VGPR bank state save in gfx12.1 trap handlerJay Cornwall
S_SETREG_IMM32_B32 does not apply a mask to the MODE bank bits. SRC2 is consequently unconditonally cleared during context save. Use S_SETREG_B32 instead to preserve SRC2. Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-12 13:47:19 +0000