summaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Expand)Author
2015-03-17drm/i915: Update prop, int co-eff and gain threshold for CHVVijay Purushothaman
2015-03-17drm/i915: Initialize CHV digital lock detect thresholdVijay Purushothaman
2015-03-17drm/i915: Disable M2 frac division for integer caseVijay Purushothaman
2015-03-17drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven
2015-03-17drm/i915: Use crtc->state->active in ilk/skl watermark calculations (v3)Matt Roper
2015-03-17drm/i915: Update intel_crtc_active() to use state values (v2)Matt Roper
2015-03-17drm/i915: Exit early from psr_status if PSR is not supported by the deviceDamien Lespiau
2015-03-17drm/i915: Fix chv cdclk supportVille Syrjälä
2015-03-17drm/i915: Allow pixel clock up to 95% of cdclk on CHVVille Syrjälä
2015-03-17drm/i915/skl: port A fuse straps don't work on early SKL steppingsJesse Barnes
2015-03-17drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau
2015-03-17drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau
2015-03-17drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau
2015-03-17drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau
2015-03-17drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau
2015-03-17drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau
2015-03-17drm/i915/chv: Add CHV HW status to SSEU statusJeff McGee
2015-03-17drm/i915/chv: Determine CHV slice/subslice/EU infoJeff McGee
2015-03-17drm/i915: Make sure PND deadline mode is enabled on VLV/CHVVille Syrjälä
2015-03-17drm/i915: Read out display FIFO size on VLV/CHVVille Syrjälä
2015-03-17drm/i915: Pass plane to vlv_compute_drain_latency()Ville Syrjälä
2015-03-17drm/i915: Reorganize VLV DDL setupVille Syrjälä
2015-03-17drm/i915: Hide VLV DDL precision handlingVille Syrjälä
2015-03-17drm/i915: Simplify VLV drain latency computationVille Syrjälä
2015-03-17drm/i915: Kill DRAIN_LATENCY_PRECISION_* definesVille Syrjälä
2015-03-17drm/i915: Reduce CHV DDL multiplier to 16/8Ville Syrjälä
2015-03-17drm/i915: Disable the mmio.debug WARN after it firesChris Wilson
2015-03-17drm/i915: fix simple_return.cocci warningskbuild test robot
2015-03-17drm/i915: Do both mt and gen6 style forcewake reset on ivb probeMika Kuoppala
2015-03-17drm/i915: Remove ironlake rc6 supportJohn Harrison
2015-03-17drm/i915: Don't clobber plane state on internal disablesMatt Roper
2015-03-17drm/i915: Setup all page directories for gen8Mika Kuoppala
2015-03-17drm/i915/skl: Program PLL for edp1.4 intermediate frequenciesSonika Jindal
2015-03-17drm/i915/skl: Add support for edp 1.4 intermediate frequenciesSonika Jindal
2015-03-17drm/i915/skl: Read sink supported rates from edp panelSonika Jindal
2015-03-17drm/i915: add frontbuffer tracking to FBCPaulo Zanoni
2015-03-17drm/i915: Fixing mutex deadlock window at eDP DRRSRamalingam C
2015-03-17drm/i915: Add debugfs entry for DRRSVandana Kannan
2015-03-17drm/i915: Add I915_PARAM_REVISIONNeil Roberts
2015-03-17drm/i915: Improve staged config loggingAnder Conselvan de Oliveira
2015-03-17drm/i915: Add a for_each_intel_connector macroAnder Conselvan de Oliveira
2015-03-17drm/i915: Set crtc backpointer when duplicating crtc stateAnder Conselvan de Oliveira
2015-03-17drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHzVille Syrjälä
2015-03-17drm/i915: also do frontbuffer tracking on pwritesPaulo Zanoni
2015-03-17drm/i915: pass which operation triggered the frontbuffer trackingPaulo Zanoni
2015-03-17Revert "drm/i915: Switch planes from transitional helpers to full atomic help...Daniel Vetter
2015-03-17drm/i915/skl: Only use the 800mV+2bB HDMI translation entryDamien Lespiau
2015-03-17drm/i915: Make for_each_sprite() take dev_priv as argumentDamien Lespiau
2015-03-17drm/i915: Make for_each_plane() take dev_priv as argumentDamien Lespiau
2015-03-17drm/i915: Remove irq-related FIXME in reset codeDaniel Vetter
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-05 02:35:03 +0000