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path: root/drivers/gpu/drm
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2026-01-05drm/amd/pm: fix wrong pcie parameter on navi1xYang Wang
fix wrong pcie dpm parameter on navi1x Fixes: 1a18607c07bb ("drm/amd/pm: override pcie dpm parameters only if it is necessary") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4671 Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Co-developed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd: Drop "amdgpu kernel modesetting enabled" messageMario Limonciello (AMD)
The behavior for amdgpu was changed with commit e00e5c223878 ("drm/amdgpu: adjust drm_firmware_drivers_only() handling") to potentially allow loading even if nomodeset was set, so the message is no longer accurate. Just drop it to avoid confusion. Fixes: e00e5c223878 ("drm/amdgpu: adjust drm_firmware_drivers_only() handling") Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Add address checking for unirasJinzhou Su
Add address checking for uniras Signed-off-by: Jinzhou Su <jinzhou.su@amd.com> Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/radeon: Remove __counted_by from ClockInfoArray.clockInfo[]Alex Deucher
clockInfo[] is a generic uchar pointer to variable sized structures which vary from ASIC to ASIC. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4374 Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add support for MMHUB IP version 3.4.0Tim Huang
This initializes MMHUB IP version 3.4.0. v2: squash in clients table update (Alex) Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add support for HDP IP version 6.1.1Tim Huang
This initializes HDP IP version 6.1.1. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add support for IH IP version 6.1.1Tim Huang
This initializes IH IP version 6.1.1. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add support for NBIO IP version 7.11.4Tim Huang
This initializes NBIO IP version 7.11.4. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add support for SDMA IP version 6.1.4Tim Huang
This initializes SDMA IP version 6.1.4. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add support for GC IP version 11.5.4Tim Huang
This initializes GC IP version 11.5.4. v2: squash in RLC offset fix Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Fix xcc_id input for soc_v1_0_grbm_selectHawking Zhang
Ensure the GRBM_GFX_CNTL is programmed correctly Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Do not initialize imu callback for vfHawking Zhang
Not needed in guest environment Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: make normalize reg addr to common func for soc v1Likun Gao
Normalize registers address to local xcc address for sdma v7_1. Merge normalize register address function to an common function for soc v1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Setup MTYPE on SOC models for GFX 12.1Mukul Joshi
Fix it to apply for all models. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Report correct compute partition mode on GFX 12.1Mukul Joshi
PSP programs the NBIO partition status register. In the absence of PSP, read the current compute partition from the GFX IMU register instead of NBIO. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Send MES packets on correct XCC on GFX 12.1Mukul Joshi
Send the Set_Shader_Debugger packet on the correct MES pipe when partition mode is set to non-SPX mode. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Add/remove queues on the correct XCC on GFX 12.1Mukul Joshi
On GFX 12.1, pass the xcc id of the master XCC to choose the correct MES Pipe to send the add_queue/remove_queue requests to MES. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Don't partition VMID space on GFX 12.1Mukul Joshi
There is no need to partition VMID space on GFX 12.1 when operating in CPX mode as SDMA is not sharing MMHUB on GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Rework MES initialization on GFX 12.1Mukul Joshi
Currently, only SPX mode works on GFX 12.1. This patch reworks the MES initialization to get other non-SPX modes working. For example, for CPX mode, coop_enable bit needs to be set to 0. The shared command buffer initialization is also not needed in CPX mode. The shared command buffer initialization needs further improvements which will be handled in later patches. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Use correct MES pipe in non-SPX mode on GFX 12.1Mukul Joshi
On GFX 12.1, use the correct MES pipe instance for readiness before sending MES commands on that pipe. Additionally, send the TLB requests on the correct MES pipe in non-SPX modes. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: adjust xcc_id program logic for sdma v7_1Likun Gao
Adjust program logic for sdam v7_1, only use physical xcc_id when program register to support compute partition. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: adjust xcc logic for gfxhub v12_1Likun Gao
Adjust xcc_id logic to only use physical xcc_id when program register, (use logic xcc_id by default), to fit for compute partition. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: adjust xcc_cp_resume function for gfx_v12_1Likun Gao
Adjust gfx_v12_1_xcc_cp_resume function to program cp resume per xcc_id (logic xcc number) to fix for xcp_resume. V2: Allocate compute microcode bo when sw init Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Add SDMA queue quantum support for GFX12.1Gang Ba
program SDMAx_QUEUEx_SCHEDULE_CNTL for context switch due to quantum in KFD for GFX12.1 Signed-off-by: Gang Ba <Gang.Ba@amd.com> Reviewed-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Set SDMA_QUEUEx_IB_CNTL/SWITCH_INSIDE_IBGang Ba
When submitting MQD to CP, set SDMA_QUEUEx_IB_CNTL/SWITCH_INSIDE_IB bit so it'll allow SDMA preemption if there is a massive command buffer of long-running SDMA commands. Signed-off-by: Gang Ba <Gang.Ba@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: disable burst for gfx v12_1Likun Gao
Disable burst in GL1A and GLARBA for gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Setup Retry based thrashing prevention on GFX 12.1Mukul Joshi
Enable the new UTCL0 retry-based thrashing prevention on GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Program IH_VMID_LUT_INDEX register on GFX 12.1Mukul Joshi
For querying VMID <-> PASID mapping on GFX 12.1, we need to first program the IH_VMID_LUT_INDEX before fetching the LUT mapping. Without this TLB flush may not work. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/ras: Support physical address convertJinzhou Su
Support physical address convert to current NPS pages in uniras. Signed-off-by: Jinzhou Su <jinzhou.su@amd.com> Reviewed-by: YiPeng Chai <YiPeng.Chai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu/gfx_v12_1: add mqd_stride_size input parameterJack Xiao
mqd_stride_size is used to calculate the next mqd offset for cooperative dispatch. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdkfd: Fix a couple of spelling mistakesColin Ian King
There are a couple of spelling mistakes, one in a pr_warn message and one in a seq_printf message. Fix these. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Describe @AMD_IP_BLOCK_TYPE_RAS in amd_ip_block_type enumBagas Sanjaya
Sphinx reports kernel-doc warning: WARNING: ./drivers/gpu/drm/amd/include/amd_shared.h:113 Enum value 'AMD_IP_BLOCK_TYPE_RAS' not described in enum 'amd_ip_block_type' Describe the value to fix it. Fixes: 7169e706c82d ("drm/amdgpu: Add ras module ip block to amdgpu discovery") Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Don't use kernel-doc comment in dc_register_software_state ↵Bagas Sanjaya
struct Sphinx reports kernel-doc warning: WARNING: ./drivers/gpu/drm/amd/display/dc/dc.h:2796 This comment starts with '/**', but isn't a kernel-doc comment. Refer to Documentation/doc-guide/kernel-doc.rst * Software state variables used to program register fields across the display pipeline Don't use kernel-doc comment syntax to fix it. Fixes: b0ff344fe70c ("drm/amd/display: Add interface to capture expected HW state from SW state") Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Reduce number of arguments of dcn30's ↵Nathan Chancellor
CalculateWatermarksAndDRAMSpeedChangeSupport() CalculateWatermarksAndDRAMSpeedChangeSupport() has a large number of parameters, which must be passed on the stack. Most of the parameters between the two callsites are the same, so they can be accessed through the existing mode_lib pointer, instead of being passed as explicit arguments. Doing this reduces the stack size of dml30_ModeSupportAndSystemConfigurationFull() from 1912 bytes to 1840 bytes building for x86_64 with clang-22, helping stay under the 2048 byte limit for display_mode_vba_30.c. Additionally, now that there is a pointer to mode_lib->vba available, use 'v' consistently throughout the entire function. Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Reduce number of arguments of dcn30's ↵Nathan Chancellor
CalculatePrefetchSchedule() After an innocuous optimization change in clang-22, dml30_ModeSupportAndSystemConfigurationFull() is over the 2048 byte stack limit for display_mode_vba_30.c. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3529:6: warning: stack frame size (2096) exceeds limit (2048) in 'dml30_ModeSupportAndSystemConfigurationFull' [-Wframe-larger-than] 3529 | void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) | ^ With clang-21, this function was already close to the limit: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3529:6: warning: stack frame size (1912) exceeds limit (1586) in 'dml30_ModeSupportAndSystemConfigurationFull' [-Wframe-larger-than] 3529 | void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) | ^ CalculatePrefetchSchedule() has a large number of parameters, which must be passed on the stack. Most of the parameters between the two callsites are the same, so they can be accessed through the existing mode_lib pointer, instead of being passed as explicit arguments. Doing this reduces the stack size of dml30_ModeSupportAndSystemConfigurationFull() from 2096 bytes to 1912 bytes with clang-22. Closes: https://github.com/ClangBuiltLinux/linux/issues/2117 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/display: Apply e4479aecf658 to dmlNathan Chancellor
After an innocuous optimization change in clang-22, allmodconfig (which enables CONFIG_KASAN and CONFIG_WERROR) breaks with: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1724:6: error: stack frame size (3144) exceeds limit (3072) in 'dml32_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] 1724 | void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) | ^ With clang-21, this function was already pretty close to the existing limit of 3072 bytes. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.c:1724:6: error: stack frame size (2904) exceeds limit (2048) in 'dml32_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] 1724 | void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) | ^ A similar situation occurred in dml2, which was resolved by commit e4479aecf658 ("drm/amd/display: Increase sanitizer frame larger than limit when compile testing with clang") by increasing the limit for clang when compile testing with certain sanitizer enabled, so that allmodconfig (an easy testing target) continues to work. Apply that same change to the dml folder to clear up the warning for allmodconfig, unbreaking the build. Closes: https://github.com/ClangBuiltLinux/linux/issues/2135 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/radeon : Use devm_i2c_add_adapter instead of i2c_add_adapterErick Karanja
Replace i2c_add_adapter() with devm_i2c_add_adapter() and remove all associated cleanup, as devm_i2c_add_adapter() handles adapter teardown automatically. Signed-off-by: Erick Karanja <karanja99erick@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Update AMDGPU_INFO_UQ_FW_AREAS query for sdmaAlex Deucher
Add a query for sdma queues. Userspace can use this to query the size of the CSA buffers for sdma user queues. Proposed userspace: https://gitlab.freedesktop.org/yogeshmohan/mesa/-/commits/userq_query Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: Update AMDGPU_INFO_UQ_FW_AREAS query for computeAlex Deucher
Add a query for compute queues. Userspace can use this to query the size of the EOP buffers for compute user queues. Proposed userspace: https://gitlab.freedesktop.org/yogeshmohan/mesa/-/commits/userq_query Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/i915/cdclk: Implement Wa_13012396614Gustavo Sousa
A new workaround was defined for Xe3_LPD, which requires a tweak on how we handle MDCLK selection. Implement it. Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Link: https://patch.msgid.link/20251222-display-wa-13012396614-timing-of-mdclk-source-selection-v1-2-a2f7e9447f7a@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-01-05drm/i915/display_wa: Keep enum intel_display_wa sortedGustavo Sousa
For a consistent way of updating enum intel_display_wa, let's sort it by lineage number and add a comment asking for future updates to keep it sorted. In the same way, let's also keep __intel_display_wa() sorted. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20251222-display-wa-13012396614-timing-of-mdclk-source-selection-v1-1-a2f7e9447f7a@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-01-05drm/panel: edp: add BOE NV140WUM-T08 panelHans de Goede
Add powerseq timing info for the BOE NV140WUM-T08 panel used on Lenovo Thinkpad T14s gen 6 (Snapdragon X1 Elite) laptops. edid-decode (hex): 00 ff ff ff ff ff ff 00 09 e5 26 0c 00 00 00 00 0a 21 01 04 a5 1e 13 78 03 d6 62 99 5e 5a 8e 27 25 53 58 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 33 3f 80 dc 70 b0 3c 40 30 20 36 00 2e bc 10 00 00 1a 00 00 00 fd 00 28 3c 4c 4c 10 01 0a 20 20 20 20 20 20 00 00 00 fe 00 42 4f 45 20 43 51 0a 20 20 20 20 20 20 00 00 00 fe 00 4e 56 31 34 30 57 55 4d 2d 54 30 38 0a 00 fa Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patch.msgid.link/20260105155134.83266-1-johannes.goede@oss.qualcomm.com
2026-01-05drm/xe/i2c: Force polling mode in survivabilityRaag Jadav
SGUnit interrupts are not initialized in survivability. Force I2C controller to polling mode while in survivability. v2: Use helper function instead of manual check (Riana) Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Link: https://patch.msgid.link/20260105080750.16605-1-raag.jadav@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-01-05drm/meson: venc: add support for HDMI DMT modes up to 3840x2160Martin Blumenstingl
Commit 5d0bfe448481 ("drm/meson: Add HDMI 1.4 4k modes") added support for HDMI 1.4 4k modes, which is what TVs need. For computer monitors the code is using the DMT code-path, which ends up in meson_venc_hdmi_supported_mode(), which does not allow the 4k modes yet. The datasheet for all supported SoCs mentions "4Kx2K@60". It's not clear whether "4K" here means 3840 or 4096 pixels. Allow resolutions up to 3840x2160 pixels (including middle steps, such as WQHD at 2560x1440 pixels) so they can be used with computer monitors (using the DMT code-path in the driver). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251108134236.1299630-1-martin.blumenstingl@googlemail.com
2026-01-05drm/panic: Add kunit tests for drm_panicJocelyn Falempe
Add kunit tests for drm_panic. They check that drawing the panic screen doesn't crash, but they don't check the correctness of the resulting image. Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://patch.msgid.link/20251216082524.115980-3-jfalempe@redhat.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2026-01-05drm/panic: Rename draw_panic_static_* to draw_panic_screen_*Jocelyn Falempe
I called them "static" because the panic screen is drawn only once, but this can be confused with the static meaning in C. Also remove some unnecessary braces in draw_panic_dispatch(). No functionnal change. Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patch.msgid.link/20251216082524.115980-2-jfalempe@redhat.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2026-01-05drm/i915/ltphy: Provide protection against unsupported modesSuraj Kandpal
We need to make sure we return some port clock in case we have unsupported LT PHY modes or if we were not able to read the LT PHY state for whatever reason and the mode ends up being 0. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105055937.136522-3-suraj.kandpal@intel.com
2026-01-05drm/i915/ltphy: Compare only certain fields in state verify functionSuraj Kandpal
Verify only the config[0,2] fields in the LT PHY state since these are the only reliable values we can get back when we read the VDR registers. The reason being that the state does not persist for other VDR registers when power gating comes into picture. Though not ideal this change does not hit us badly in perspective of how we use the compare function to decide if fastset is required or if we wrote the state correctly. VDR0_CONFIG and VDR1_CONFIG hold the values that indicate the PLL operating mode and link rate which is usually what we need to check if something has changed or not. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105055937.136522-2-suraj.kandpal@intel.com
2026-01-05drm/i915/ltphy: Remove state verification for LT PHY fieldsSuraj Kandpal
Currently we do state verification for all VDR Registers. Remove LT PHY State verification for all VDR register fields other than VDR0_CONFIG and VDR2_CONFIG. The reason being that VDR0_CONFIG and VDR2_CONFIG are the only reliable shadow register which hold onto their values over the course of power gatings which happen internally due to features like PSR/PR. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260105055937.136522-1-suraj.kandpal@intel.com
2026-01-04drm: pl111: fix build regressionArnd Bergmann
The drm_info() function requires the drm/drm_print.h header to be included first: In file included from drivers/gpu/drm/pl111/pl111_nomadik.c:7: drivers/gpu/drm/pl111/pl111_nomadik.h:11:32: error: 'struct drm_device' declared inside parameter list will not be visible outside of this definition or declaration [-Werror] 11 | void pl111_nomadik_init(struct drm_device *dev); | ^~~~~~~~~~ drivers/gpu/drm/pl111/pl111_nomadik.c: In function 'pl111_nomadik_init': drivers/gpu/drm/pl111/pl111_nomadik.c:34:9: error: implicit declaration of function 'drm_info'; did you mean 'pr_info'? [-Wimplicit-function-declaration] 34 | drm_info(dev, "set Nomadik PMU mux to CLCD mode\n"); | ^~~~~~~~ | pr_info Fixes: a1542b8ca6ed ("drm: pl111: replace dev_* print functions with drm_* variants") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Eslam Khafagy <eslam.medhat1993@gmail.com> Signed-off-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20251223214915.503913-1-arnd@kernel.org
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