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path: root/drivers/gpu/drm
AgeCommit message (Expand)Author
2015-11-12drm/i915/gen9: Use dev_priv in csr functionsDaniel Vetter
2015-11-12drm/i915/gen9: Don't try to load garbage dmc firmware on resumeDaniel Vetter
2015-11-12drm/i915/gen9: Simplify csr loading failure printing.Daniel Vetter
2015-11-12drm/i915/gen9: Align line continuations in intel_csr.c.Daniel Vetter
2015-11-12drm/i915/gen9: Remove csr.state, csr_lock and related code.Daniel Vetter
2015-11-12drm/i915/gen9: move assert_csr_loaded into intel_rpm.cDaniel Vetter
2015-11-12drm/i915: use correct power domain for csr loadingDaniel Vetter
2015-11-12drm/i915/gen9: csr_init after runtime pm enableAnimesh Manna
2015-11-12drm/i915: refactor stepping info retrievalJani Nikula
2015-11-12drm/i915: constify bxt stepping infoJani Nikula
2015-11-12drm/i915: fix indentation on skl stepping infoJani Nikula
2015-11-12drm/i915: Remove redundant check in i915_gem_obj_to_vmaTvrtko Ursulin
2015-11-11drm/i915: Clean up LVDS register handling harderLukas Wunner
2015-11-11drm/i915: Move the fbdev async_schedule() into intel_fbdev.cVille Syrjälä
2015-11-11drm/i915: Do fbdev fini first during unloadVille Syrjälä
2015-11-11drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä
2015-11-10drm/i915: Setup DDI clk for MST on SKLVille Syrjälä
2015-11-10drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()Ville Syrjälä
2015-11-10drm/i915: Use intel_dp->DP in eDP PLL setupVille Syrjälä
2015-11-10drm/i915: Clean up eDP PLL state assertsVille Syrjälä
2015-11-10drm/i915: Remove ILK-A eDP PLL workaround notesVille Syrjälä
2015-11-10drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä
2015-11-10drm/i915: Hide underruns from eDP PLL and port enable on ILKVille Syrjälä
2015-11-10drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaroundVille Syrjälä
2015-11-10drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()Ville Syrjälä
2015-11-10drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPTVille Syrjälä
2015-11-10drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabledVille Syrjälä
2015-11-10drm/i915: Enable PCH FIFO underruns later on HSW+Ville Syrjälä
2015-11-10drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVBVille Syrjälä
2015-11-10drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTLVille Syrjälä
2015-11-10drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config...Ville Syrjälä
2015-11-10drm/i915: remove in_dbg_master check from intel_fbc.cPaulo Zanoni
2015-11-10drm/i915: clarify that checking the FB stride for CFB is intentionalPaulo Zanoni
2015-11-10drm/i915: remove too-frequent FBC debug messagePaulo Zanoni
2015-11-10drm/i915: refactor FBC deactivation at initPaulo Zanoni
2015-11-10drm/i915: don't disable_fbc() if FBC is already disabledPaulo Zanoni
2015-11-10drm/i915: fix the __intel_fbc_update() commentsPaulo Zanoni
2015-11-10drm/i915: use struct intel_crtc *crtc at __intel_fbc_update()Paulo Zanoni
2015-11-10drm/i915: extract crtc_is_valid() on the FBC codePaulo Zanoni
2015-11-10drm/i915: remove unnecessary check for crtc->primary->fbPaulo Zanoni
2015-11-10drm/i915: extract fbc_on_pipe_a_only()Paulo Zanoni
2015-11-10drm/i915: rename intel_fbc_nuke to intel_fbc_recompressPaulo Zanoni
2015-11-10drm/i915: remove newline from a no_fbc_reason messagePaulo Zanoni
2015-11-09drm/i915/bxt: Force port A DDI to use 4 lanesMatt Roper
2015-11-09drm/i915: Print a debug message when exceeding dotclock limit on pre-gen4Ville Syrjälä
2015-11-09drm/i915: Avoid pointer arithmetic in calculating plane surface offsetMika Kuoppala
2015-11-09drm/i915: Add dmc firmware load state and version to error stateMika Kuoppala
2015-11-09drm/i915: Add csr programming registers to dmc debugfs entryMika Kuoppala
2015-11-09drm/i915/bxt: Expose DC5 entry countMika Kuoppala
2015-11-09drm/i915/skl: Expose DC5/DC6 entry countsDamien Lespiau
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