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path: root/drivers/gpu/drm
AgeCommit message (Expand)Author
2015-03-17drm/i915/skl: Updated the i915_frequency_info debugfs functionAkash Goel
2015-03-17drm/i915: Simplify the way BC bifurcation state consistency is keptAnder Conselvan de Oliveira
2015-03-17drm/i915/skl: Updated the act_freq_mhz_show sysfs functionAkash Goel
2015-03-17drm/i915/skl: Updated the gen9_enable_rps functionAkash Goel
2015-03-17drm/i915/skl: Updated the gen6_rps_limits functionAkash Goel
2015-03-17drm/i915/skl: Restructured the gen6_set_rps_thresholds functionAkash Goel
2015-03-17drm/i915/skl: Updated the gen6_set_rps functionAkash Goel
2015-03-17drm/i915/skl: Updated the gen6_init_rps_frequencies functionAkash Goel
2015-03-17drm/i915/skl: Updated intel_gpu_freq() and intel_freq_opcode()Akash Goel
2015-03-17drm/i915/skl: Added new macrosAkash Goel
2015-03-17drm/i915: Use FW_WM() macro for older gmch platforms tooVille Syrjälä
2015-03-17drm/i915: Add polish to VLV WM shift+mask operationsVille Syrjälä
2015-03-17drm/i915: Use plane->state->fb instead of plane->fb in intel_plane_restore()Ville Syrjälä
2015-03-17drm/i915: Reduce clutter by using the local plane pointerVille Syrjälä
2015-03-17drm/i915: Remove debug prints from primary plane update funcsVille Syrjälä
2015-03-17drm/i915: Add ULL postfix to VGT_MAGIC constantDaniel Vetter
2015-03-17drm/i915: Don't assume primary & cursor are always on for wm calculation (v4)Matt Roper
2015-03-17drm/i915: Move drm_framebuffer_unreference out of struct_mutex for flipsChris Wilson
2015-03-17drm/i915: Disable DDR DVFS on CHVVille Syrjälä
2015-03-17drm/i915: Enable the maxfifo PM5 mode when appropriate on CHVVille Syrjälä
2015-03-17drm/i915: Program PFI credits for VLVVidya Srinivas
2015-03-17drm/i915: Rewrite VLV/CHV watermark codeVille Syrjälä
2015-03-17drm/i915: Make sure we invalidate frontbuffer on fbcon.Rodrigo Vivi
2015-03-17drm/i915: Update prop, int co-eff and gain threshold for CHVVijay Purushothaman
2015-03-17drm/i915: Initialize CHV digital lock detect thresholdVijay Purushothaman
2015-03-17drm/i915: Disable M2 frac division for integer caseVijay Purushothaman
2015-03-17drm/i915: Spelling s/auxilliary/auxiliary/Geert Uytterhoeven
2015-03-17drm/i915: Use crtc->state->active in ilk/skl watermark calculations (v3)Matt Roper
2015-03-17drm/i915: Update intel_crtc_active() to use state values (v2)Matt Roper
2015-03-17drm/i915: Exit early from psr_status if PSR is not supported by the deviceDamien Lespiau
2015-03-17drm/i915: Fix chv cdclk supportVille Syrjälä
2015-03-17drm/i915: Allow pixel clock up to 95% of cdclk on CHVVille Syrjälä
2015-03-17drm/i915/skl: port A fuse straps don't work on early SKL steppingsJesse Barnes
2015-03-17drm/i915/skl: Restore the DDI translation tables when enabling PW1Damien Lespiau
2015-03-17drm/i915: Remove unused condition in hsw_power_well_post_enable()Damien Lespiau
2015-03-17drm/i915/skl: Restore pipe interrupt registers after power well enablingDamien Lespiau
2015-03-17drm/i915/skl: Mirror what we do on HSW for the power well enable log messageDamien Lespiau
2015-03-17drm/i915/skl: Introduce enable_requested and is_enabled in the power well codeDamien Lespiau
2015-03-17drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe maskDamien Lespiau
2015-03-17drm/i915/chv: Add CHV HW status to SSEU statusJeff McGee
2015-03-17drm/i915/chv: Determine CHV slice/subslice/EU infoJeff McGee
2015-03-17drm/i915: Make sure PND deadline mode is enabled on VLV/CHVVille Syrjälä
2015-03-17drm/i915: Read out display FIFO size on VLV/CHVVille Syrjälä
2015-03-17drm/i915: Pass plane to vlv_compute_drain_latency()Ville Syrjälä
2015-03-17drm/i915: Reorganize VLV DDL setupVille Syrjälä
2015-03-17drm/i915: Hide VLV DDL precision handlingVille Syrjälä
2015-03-17drm/i915: Simplify VLV drain latency computationVille Syrjälä
2015-03-17drm/i915: Kill DRAIN_LATENCY_PRECISION_* definesVille Syrjälä
2015-03-17drm/i915: Reduce CHV DDL multiplier to 16/8Ville Syrjälä
2015-03-17drm/i915: Disable the mmio.debug WARN after it firesChris Wilson
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