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path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)Author
2015-09-01drm/i915: Preserve SSC earlierLukas Wunner
2015-08-31drm/i915/skl: Adding DDI_E power well domainXiong Zhang
2015-08-31drm/i915: eDP can be present on DDI-ERodrigo Vivi
2015-08-31drm/i915/skl: Enable DDI-ERodrigo Vivi
2015-08-31drm/i915: Enable HDMI on DDI-EXiong Zhang
2015-08-31drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6Imre Deak
2015-08-31drm/i915: Check DP link status on long hpd tooVille Syrjälä
2015-08-28drm/i915: set CDCLK if DPLL0 enabled during resuming from S3Gary Wang
2015-08-28drm/i915: Update DRIVER_DATE to 20150828Daniel Vetter
2015-08-26Partially revert "drm/i915: Use full atomic modeset."Maarten Lankhorst
2015-08-26drm/i915: gen 9 can check for unclaimed registers tooPaulo Zanoni
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä
2015-08-26drm/i915: Force common lane on for the PPS kick on CHVVille Syrjälä
2015-08-26drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä
2015-08-26drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä
2015-08-26drm/i915: Make some string arrays constVille Syrjälä
2015-08-26drm/i915: Use ARRAY_SIZE() instead of hand rolling itVille Syrjälä
2015-08-26drm/i915: Fix some gcc warningsVille Syrjälä
2015-08-26drm/i915/bxt: Use correct live status register for BXT platformJani Nikula
2015-08-26drm/i915: split g4x_digital_port_connected to g4x and vlv variantsJani Nikula
2015-08-26drm/i915: split ibx_digital_port_connected to ibx and cpt variantsJani Nikula
2015-08-26drm/i915: add common intel_digital_port_connected functionJani Nikula
2015-08-26drm/i915: add MISSING_CASE annotation to ibx_digital_port_connectedJani Nikula
2015-08-26drm/i915: make g4x_digital_port_connected return boolean statusJani Nikula
2015-08-26drm/i915: move ibx_digital_port_connected to intel_dp.cJani Nikula
2015-08-26drm/i915: DVO pixel clock checkMika Kahola
2015-08-26drm/i915: DSI pixel clock checkMika Kahola
2015-08-26drm/i915: LVDS pixel clock checkMika Kahola
2015-08-26drm/i915: Store max dotclockMika Kahola
2015-08-26drm/i915: Add vlv_dport_to_phy()Ville Syrjälä
2015-08-26drm/i915: Move VLV/CHV prepare_pll laterVille Syrjälä
2015-08-26drm/i915: Add locking around chv_phy_control_init()Ville Syrjälä
2015-08-26drm/i915: Move DPIO port init earlierVille Syrjälä
2015-08-26drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer dis...Ville Syrjälä
2015-08-26drm/i915: Always program unique transition scale for CHVVille Syrjälä
2015-08-26drm/i915: Always program m2 fractional value on CHVVille Syrjälä
2015-08-26drm/i915: fix driver's versions of WARN_ON & WARN_ON_ONCEDave Gordon
2015-08-26drm/i915: Put back lane_count into intel_dp and add link_rate tooVille Syrjälä
2015-08-26drm/i915/bxt: don't allow cached GEM mappings on A steppingImre Deak
2015-08-26drm/i915/bxt: work around HW coherency issue when accessing GPU seqnoImre Deak
2015-08-26drm/i915/skl: enable DDI-E hotplugXiong Zhang
2015-08-26drm/i915: Fix build warning on 32-bitThierry Reding
2015-08-26drm/i915/skl: Update DDI buffer translation programming.Rodrigo Vivi
2015-08-26drm/i915: Also call frontbuffer flip when disabling planes.Rodrigo Vivi
2015-08-26drm/i915: Change SRM, LRM instructions to use correct lengthArun Siluvery
2015-08-24drm/i915: Allow parsing of variable size child device entries from VBTDavid Weinehall
2015-08-24drm/i915: fix link rates reported for SKLThulasimani,Sivakumar
2015-08-24drm/i915: fix VBT parsing for SDVO child device mappingJani Nikula
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