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path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)Author
2014-08-08drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat
2014-08-08drm/i915: Round-up clock and limit drain latencyGajanan Bhat
2014-08-08drm/i915: Generalize drain latency computationGajanan Bhat
2014-08-08drm/i915: Free pending page flip events at .preclose()Ville Syrjälä
2014-08-08drm/i915: clean up PPGTT checking logicJesse Barnes
2014-08-08drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä
2014-08-08drm/i915: Hack to tie both common lanes together on chvVille Syrjälä
2014-08-08drm/i915: Add cherryview_update_wm()Ville Syrjälä
2014-08-08drm/i915: Update DDL only for current CRTCGajanan Bhat
2014-08-08drm/i915: Parametrize VLV_DDL registersVille Syrjälä
2014-08-08drm/i915: Fill out the FWx watermark register definesVille Syrjälä
2014-08-08drm/i915: Add rotation property for spritesVille Syrjälä
2014-08-08drm/i915: Make intel_plane_restore() return an errorVille Syrjälä
2014-08-08drm/i915: Add 180 degree sprite rotation supportVille Syrjälä
2014-08-08drm/i915: Introduce a for_each_intel_encoder() macroDamien Lespiau
2014-08-08drm/i915: Demote the DRRS messages to debug messagesDamien Lespiau
2014-08-08drm/i915: remove duplicate register definesPaulo Zanoni
2014-08-08drm/i915: Remove now useless comments about the translation valuesDamien Lespiau
2014-08-08drm/i915/bdw: Remove the HDMI/DVI entry from the DP/eDP/FDI tablesDamien Lespiau
2014-08-08drm/i915/bdw: Provide the BDW specific HDMI buffer translation tableDamien Lespiau
2014-08-08drm/i915: Gather the HDMI level shifter logic into one placeDamien Lespiau
2014-08-08drm/i915: Introduce FBC False Color for debug purposes.Rodrigo Vivi
2014-08-08drm/i915: Align intel_dsi*.c files a bitDaniel Vetter
2014-08-08drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar
2014-08-08drm/i915: Clarify CHV swing margin/deemph bitsVille Syrjälä
2014-08-08drm/i915: Call intel_{dp, hdmi}_prepare for chvVille Syrjälä
2014-08-08drm/i915: Split chv_update_pll() apartVille Syrjälä
2014-08-08drm/i915: Leave DPLL ref clocks onVille Syrjälä
2014-08-08drm/i915: Disable cdclk changes for chv until Punit is readyVille Syrjälä
2014-08-08drm/i915: Add cdclk change support for chvVille Syrjälä
2014-08-08d rm/i915: freeze display before the interrupts and GTPaulo Zanoni
2014-08-08drm/i915: Make ddi_clock_gate() HSW/BDW specificDaniel Vetter
2014-08-08drm/i915: Split the CDCLK retrieval per-platformDamien Lespiau
2014-08-08drm/i915: Make intel_ddi_calculate_wrpll() HSW/BDW specificDamien Lespiau
2014-08-08drm/i915: Split the BDW/HSW specific shared pll selectionDamien Lespiau
2014-08-08drm/i915: Fix stale comment for intel_ddi_pll_select()Damien Lespiau
2014-08-08drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDWDamien Lespiau
2014-08-08drm/i915: Extract the HSW/BDW shared dpll init codeDamien Lespiau
2014-08-08drm/i915: Extract the HSW DDI selection code into its own functionDamien Lespiau
2014-08-08drm/i915: Add a space to the shared DPLL debug messageDamien Lespiau
2014-08-08drm/i915: Specify when the PLL hw state fields are validDamien Lespiau
2014-08-08drm/i915: Add DP training pattern 3 for CHVVille Syrjälä
2014-08-08drm/i915: Split a few long debug printsVille Syrjälä
2014-08-08drm/i915: Fix read back of plane stride registerRafael Barbalho
2014-08-08drm/i915: Add chv port D TX wellsVille Syrjälä
2014-08-08drm/i915: Add chv port B and C TX wellsVille Syrjälä
2014-08-08drm/i915: Add per-pipe power wells for chvVille Syrjälä
2014-08-08drm/i915: Add disp2d power well for chvVille Syrjälä
2014-08-08drm/i915: Kill intel_reset_dpio()Ville Syrjälä
2014-08-08drm/i915: Add chv cmnlane power wellsVille Syrjälä
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