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Add devicetree bindings for the ADL8113 Low Noise Amplifier.
The bindings include support for specifying gain values of external
amplifiers connected to the two external bypass paths (A and B). These
optional properties allow the gain values to be selectable via the
hardwaregain attribute, enabling complete devicetree description of
the signal chain including external components.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Add support for clock provider.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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The s32g2 and s32g3 NXP platforms have two instances of a Successive
Approximation Register ADC. It supports the raw, trigger and scan
modes which involves the DMA. Add their descriptions.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Add device tree bindings documentation for the Texas Instruments
ADS131M0x analog-to-digital converters. This family includes the ADS131M02,
ADS131M03, ADS131M04, ADS131M06, and ADS131M08 variants.
These variants differ primarily in the number of supported channels
(2, 3, 4, 6, and 8, respectively), which requires separate compatible
strings to validate the channel nodes.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A small collection of fixes for various SPI drivers, plus a relaxation
of constraints in the DT for the DesignWare controller to reflect
hardware that's been seen.
There's several fixes for the Cadence QuadSPI driver since a fix
during the last release made some existing issues with error handling
during probe more readily visible"
* tag 'spi-fix-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: mt65xx: Use IRQF_ONESHOT with threaded IRQ
spi: dt-bindings: snps,dw-abp-ssi: Allow up to 16 chip-selects
spi: cadence-quadspi: Fix clock disable on probe failure path
spi: cadence-quadspi: Add error logging for DMA request failure
spi: fsl-cpm: Check length parity before switching to 16 bit mode
spi: mpfs: Fix an error handling path in mpfs_spi_probe()
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Lite board
Append "starfive,jh7110" compatible to VisionFive 2 Lite and VisionFive 2
Lite eMMC boards in the least-compatible end of the list.
Appending "starfive,jh7110" reduces the number of compatible strings to
check in the OpenSBI platform driver. JH-7110S SoC on these boards is the
same as JH-7110 SoC however rated for thermal, voltage, and frequency
characteristics for a maximum of 1.25GHz operation.
Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/
Suggested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: E Shattow <e@freeshell.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC host fixes from Ulf Hansson:
- sdhci-esdhc-imx: Fix build problem dependency
- sdhci-of-arasan: Increase card-detect stable timeout to 2 seconds
- sdhci-of-aspeed: Fix DT doc for missing properties
* tag 'mmc-v6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci-esdhc-imx: add alternate ARCH_S32 dependency to Kconfig
mmc: sdhci-of-arasan: Increase CD stable timeout to 2 seconds
dt-bindings: mmc: sdhci-of-aspeed: Switch ref to sdhci-common.yaml
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The PCI subsystem links an endpoint Device Tree node to its corresponding
pci_dev structure only if the Bus/Device/Function (BDF) encoded in the
'reg' property matches the actual hardware topology.
Add the 'reg' property and mark it as required to ensure proper binding
between the device_node and the pci_dev.
Update the example to reflect this requirement.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/b58bfcd957b2270fcf932d463f2db534b2ae1a6d.1766077285.git.andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The CTCU device for monaco shares the same configurations as SA8775p. Add
a fallback to enable the CTCU for monaco to utilize the compitable of the
SA8775p.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20251103-enable-ctcu-for-monaco-v4-1-92ff83201584@oss.qualcomm.com
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clocks
Commit 8a55fbe4c94d ("dt-bindings: interconnect: add reg and clocks
properties to enable QoS on sa8775p") claims that all interconnects have
clocks and MMIO address space, but that is just not true. Only few
have. Bindings should restrict properties and should not allow
specifying non-existing hardware description, so fix missing constraints
for 'reg' and 'clocks'.
Fixes: 8a55fbe4c94d ("dt-bindings: interconnect: add reg and clocks properties to enable QoS on sa8775p")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251129094612.16838-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Append rt8092 compatible in rt5739 document.
Compared to rt5739, RT8092 can offer up to 4A output current.
Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
Link: https://patch.msgid.link/9b67b2d2b4268d356f41ae2d0c3202e7813ea6b1.1766125676.git.cy_huang@richtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add descriptions for the Zilsd (Load/Store pair instructions) and
Zclsd (Compressed Load/Store pair instructions) ISA extensions
which were ratified in commit f88abf1 ("Integrating load/store
pair for RV32 with the main manual") of the riscv-isa-manual.
Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20250826162939.1494021-2-pincheng.plct@isrc.iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
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Document x1e80100 compatible for the True Random Number Generator.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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Add a pattern for sdram channel node name.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-5-a033ac5144da@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Add in the memory channel binding the DDR4 compatible to support DDR4
memory channel.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-4-a033ac5144da@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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LPDDR, DDR and so SDRAM channels exist and share the same properties, they
have a compatible, ranks, and an io-width.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-3-a033ac5144da@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Introduce JEDEC compliant DDR bindings, that use new memory-props binding.
The DDR4 compatible can be made of explicit vendor names and part
numbers or be of the form "ddrX-YYYY,AAAA...-ZZ" when associated with an
SPD, where (according to JEDEC SPD4.1.2.L-6):
- YYYY is the manufacturer ID
- AAAA... is the part number
- ZZ is the revision ID
The former form is useful when the SDRAM vendor and part number are
known, for example, when memory is soldered on the board.
The latter form is useful when SDRAM nodes are created at runtime by
boot firmware that doesn't have access to static part number information.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-2-a033ac5144da@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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LPDDR and DDR bindings are SDRAM types and are likely to share the same
properties (at least for density, io-width and reg).
To avoid bindings duplication, factorise the properties.
The compatible description has been updated because the MR (Mode
registers) used to get manufacturer ID and revision ID are not present
in case of DDR.
Those information should be in a SPD (Serial Presence Detect) EEPROM in
case of DIMM module or are known in case of soldered memory chips as
they are in the datasheet of the memory chips.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>
Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-1-a033ac5144da@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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In FPGA Development boards with GPIOs we use the opencores gpio verilog
rtl. This is compatible with the gpio-mmio. Add the compatible string
to allow as below.
Example:
gpio0: gpio@91000000 {
compatible = "opencores,gpio", "brcm,bcm6345-gpio";
reg = <0x91000000 0x1>, <0x91000001 0x1>;
reg-names = "dat", "dirout";
gpio-controller;
#gpio-cells = <2>;
status = "okay";
};
Link: https://opencores.org/projects/gpio
Signed-off-by: Stafford Horne <shorne@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20251217080843.70621-2-shorne@gmail.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
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Update the OSS email addresses across all Coresight documents, as the
previous addresses have been deprecated.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250902042143.1010-1-jie.gan@oss.qualcomm.com
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TCAL6408 and TCAL6416 supports latchable inputs and maskable interrupt.
add compatibles ti,tcal6408 and ti,tcal6416
The TI variants has the same programming model as the NXP PCAL6408 and
PCAL6416, but supports other supply voltages.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Link: https://lore.kernel.org/r/20251216-wip-jremmet-tcal6416rtw-v2-2-6516d98a9836@phytec.de
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
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Merge series from CL Wang <cl634@andestech.com>:
This series adds support for the Andes ATCSPI200 SPI controller.
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Merge series from Haibo Chen <haibo.chen@nxp.com>:
XSPI is a flexible SPI host controller which supports up to
2 external devices (2 CS). It support Single/Dual/Quad/Octal
mode data transfer.
The difference between XSPI and Flexspi is XSPI support
multiple independent execution environments (EENVs) for HW
virtualization with some limitations. Each EENV has its own
interrupt and its own set of programming registers that exists
in a specific offset range in the XSPI memory map.
The main environment (EENV0) address space contains all of the
registers for controlling EENV0 plus all of the general XSPI
control and programming registers. The register mnemonics for
the user environments (EENV1 to EENV4) have "_SUB_n" appended
to the mnemonic for the corresponding main-environment register.
Current driver based on EENV0, which means system already give
EENV0 right to linux.
This driver use SPI memory interface of the SPI framework to issue
flash memory operations. Tested this driver with mtd_debug and
UBIFS on NXP i.MX943 EVK board which has one MT35XU512ABA spi nor
flash. NOw this driver has the following key features:
- Support up to OCT DDR mode
- Support AHB read
- Support IP read and IP write
- Support two CS
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On Qualcomm Kaanapali platform, IMEM is a block of SRAM shared across
multiple IP blocks which can falk back to "mmio-sram". Documnent it and
its child node "qcom,pil-reloc-info" which is used for collecting
remoteproc ramdumps.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251123-knp-soc-binding-v4-1-42b349a66c59@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Controller
Add a compatible for the Power Domain Controller on Kaanapali platforms.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251021-knp-pdc-v2-1-a38767f5bb8e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Document the Kaanapali SoC binding and the boards which use it.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251215-knp-dts-v4-1-1541bebeb89f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Running the full 'make dt_binding_check' is slow. A shortcut is to set
DT_SCHEMA_FILES env variable to a substring of DT schema files to test.
It both limits which examples are validated and which schemas are used
to validate the examples. This is a problem because errors from other
schemas are missed. What makes validation slow is checking all examples,
so we really just need a way to test a single example.
Add a %.yaml target to validate the schema and validate the example:
make example-schema.yaml
The behavior for 'make dt_binding_check DT_SCHEMA_FILES=example-schema'
is unchanged. Really it should mirror dtbs_check and validate all the
examples with a subset of schemas, but there are lots of users of
expecting the existing behavior.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20251208224304.2907913-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
(2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
It has 6 interrupts compared to 4 on RZ/T2H.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20251129164325.209213-2-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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EHCI and OHCI controllers can be DMA coherent on some platforms, so
allow the "dma-coherent" property.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20251215212515.3318052-1-robh@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Add the "aspeed,ast2700-usb-vhub" compatible. The ast2700 vhub
controller requires an reset, so make the "resets" property
mandatory for this compatible to reflect the hardware requirement.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251128-upstream_vhub-v2-1-1fa66a5833c2@aspeedtech.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Document devicetree bindings for the Andes ATCSPI200 SPI controller.
Signed-off-by: CL Wang <cl634@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251215132349.513843-2-cl634@andestech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Document imx94 xspi that supports interface to serial flash
supporting following features:
- Single-bit SPI, Dual SPI, Quad SPI and Octal SPI.
- Single Data Rate or Double Data Rate modes.
- Direct memory mapping of all AHB memory accesses to the
chip system memory space.
- Multi-master AHB accesses with priority.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20251216-xspi-v7-1-282525220979@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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At least the Microchip Sparx5 supports up to 16 chip-selects, so
increase the maximum. The pattern for the child unit-address was
unconstrained, so update it to match the maximum number of
chip-selects.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251215230323.3634112-1-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add the compatible for another 64Kb EEPROM from Giantec.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251210-fp4-cam-prep-v1-1-0eacbff271ec@fairphone.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
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Add the compatible for Belling BL24C04A 4Kb EEPROM and BL24C16F 16Kb
EEPROM.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251202084941.1785-2-naoki@radxa.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
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Introduce new binding for the Medion SPRCHRGD 14 S1 notebook with
X1E78100 SoC.
Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251204155212.230058-5-ggo@tuxedocomputers.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add Medion AG, a German electronics company, to the list of vendor
prefixes.
Link: https://www.medion.com/
Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251204155212.230058-4-ggo@tuxedocomputers.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Introduce new binding for the TUXEDO Elite 14 Gen1 laptop with X1E78100
SoC.
Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20251204155212.230058-3-ggo@tuxedocomputers.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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TUXEDO Computers GmbH is a German supplier for computers.
Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251204155212.230058-2-ggo@tuxedocomputers.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add SM8750 compatible consistent with CAMSS CCI interfaces.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251126-add-support-for-camss-on-sm8750-v1-1-646fee2eb720@oss.qualcomm.com
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
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Add compatible string for the DesignWare-based I2C controllers present
in Mobileye Eyeq6Lplus SoC, with a fallback to the default compatible.
The same controllers are also present in the EyeQ7H, so add a compatible
for those with a fallback to the Eyeq6Lplus compatible.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251126-i2c-dw-v4-1-b0654598e7c5@bootlin.com
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Document the Last Level Cache Controller on Glymur SoC
Glymur LLCC has 12 base register regions and an additional AND, OR
broadcast region, total 14 register regions
Increase maxItems for reg and reg-names to allow 14 entries for Glymur
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251211-glymur_llcc_enablement-v3-1-43457b354b0d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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My name is stamped into maintainership for a big slew of DT
bindings. Now that it is changing, switch it over to my
kernel.org mail address, which will hopefully be stable for the
rest of my life.
Signed-off-by: Linus Walleij <linusw@kernel.org>
Link: https://patch.msgid.link/20251216-maintainers-dt-v1-1-0b5ab102c9bb@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Document the DMA controller on the Renesas RZ/V2N SoC, which is
architecturally identical to the DMAC found on the RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251125212621.267397-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
present in Renesas R-Car R8A779A0 V3U SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251106212342.2771579-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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The gate bindings have an artificial split between a "syscon" and clock
provider node. Allow "reg" properties so this split can be removed.
Reviewed-by: Chunyan Zhang <zhang.lyra@gmail.com>
Link: https://patch.msgid.link/20251029155615.1167903-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Common boolean properties need to be only allowed in the binding
(":true"), because their type is already defined by core DT schema.
Simplify dma-coherent property to match common syntax.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://patch.msgid.link/20251115122120.35315-4-krzk@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Add the HannStar HSD156JUW2 15.6" FHD (1920x1080) TFT LCD panel to
the panel-simple compatible list.
Signed-off-by: Renjun Wang <renjunw0@foxmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/tencent_8B5693A42B580AB3A5359849CCE23E67B407@qq.com
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Add compatible for used LG panel.
SW43408 is not panel, but DDIC. The panel itself is the
LG LH546WF1-ED01, so introduce combined compatible for it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20251214-pixel-3-v7-2-b1c0cf6f224d@ixit.cz
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Samsung LTL106HL02 is a simple DSI which requires only a power supply and
an optional reset gpio.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20251110091440.5251-7-clamor95@gmail.com
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