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2026-01-18dt-bindings: watchdog: qcom-wdt: Document Glymur watchdogPankaj Patil
Add devicetree binding for watchdog present on Qualcomm's Glymur SoC Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18dt-bindings: watchdog: Convert mpc8xxx-wdt to YAMLJ. Neuschäfer
Convert mpc83xx-wdt.txt to YAML to enable automatic schema validation. Signed-off-by: J. Neuschäfer <j.ne@posteo.net> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18dt-bindings: watchdog: samsung-wdt: Split if:then: and constrain moreKrzysztof Kozlowski
Binding defined two if:then: blocks covering different conditions but not fully constraining the properties per each variant: 1. "if:" to require samsung,syscon-phandle, 2. "if:" with "else:" to narrow number of clocks and require or disallow samsung,cluster-index. This still did not cover following cases: 1. Disallow samsung,syscon-phandle when not applicable, 2. Narrow samsung,cluster-index to [0, 1], for SoCs with only two clusters. Solving this in current format would lead to spaghetti code, so re-write entire "if:then:" approach into mutually exclusive cases so each SoC appears only in one "if:" block. This allows to forbid samsung,syscon-phandle for S3C6410, and narrow samsung,cluster-index to [0, 1]. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18dt-bindings: watchdog: samsung-wdt: Drop S3C2410Krzysztof Kozlowski
Samsung S3C2410 SoC was removed from Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of samsung,s3c2410-wdt compatible anymore and platform is so old, that there should be no out-of-tree users. If such existed, they would have enough of time to object dropping Samsung S3C2410 SoC removal from the kernel (which did not happen). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18dt-bindings: watchdog: samsung-wdt: Define cluster constraints top-levelKrzysztof Kozlowski
Properties should be always constrained in top-level part of the bindings, so move the samsung,cluster-index constrain from if: block. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2026-01-18dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 FRDM boardLei Xu
Introduce a new DT compatible string for the NXP i.MX95 15x15 FRDM development board, a compact and cost-effective platform based on the i.MX95 applications processor. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Signed-off-by: Lei Xu <lei.xu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2026-01-17dt-bindings: net: pcs: renesas,rzn1-miic: Add phy_link propertyLad Prabhakar
Add the renesas,miic-phy-link-active-low property to allow configuring the active level of phy_link status signals provided by the MIIC block. EtherPHY link-up and link-down status is required as a hardware IP feature independent of whether GMAC or ETHSW is used. With GMAC, link state is retrieved via MDC/MDIO and handled in software. In contrast, ETHSW exposes dedicated PHY_LINK pins that provide this information directly in hardware. These PHY_LINK signals are required not only for host-controlled traffic but also for switch-only forwarding paths where frames are exchanged between external nodes without CPU involvement. This is particularly important for redundancy protocols such as DLR (Device Level Ring), which depend on fast detection of link-down events caused by cable or port failures. Handling such events purely in software introduces latency, which is why ETHSW provides dedicated hardware PHY_LINK pins. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260112173555.1166714-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-17dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur PlatformsJingyi Wang
Document the Inter-Processor Communication Controller on the Qualcomm Kaanapali and Glymur Platforms, which will be used to route interrupts across various subsystems found on the SoC. Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-1-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-17Merge branch 'for-v6.20/dt-bindings-clk' into next/dt64Krzysztof Kozlowski
Merge clock DT binding headers from topic branch.
2026-01-17dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatiblePeter Griffin
Add dedicated compatibles for gs101 dpu sysreg controllers to the documentation. Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260113-dpu-clocks-v3-3-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-01-17Merge branch 'for-v6.20/dt-bindings-clk' into next/clkKrzysztof Kozlowski
Merge DT binding headers from topic branch, used by the driver.
2026-01-17dt-bindings: clock: google,gs101-clock: Add DPU clock management unitPeter Griffin
Add dt schema documentation and clock IDs for the Display Process Unit (DPU) clock management unit (CMU). This CMU feeds IPs such as image scaler, enhancer and compressor. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260113-dpu-clocks-v3-2-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-01-17dt-bindings: clock: google,gs101-clock: fix alphanumeric orderingPeter Griffin
Ensure children of cmu_top have alphanumeric ordering. Top is special as it feeds all the other children CMUs. This ordering then matches the clk-gs101.c file. Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260113-dpu-clocks-v3-1-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-01-17dt-bindings: arm: fsl: Document ifm VHIP4 EvalBoard v1 and v2Marek Vasut
Document ifm i.MX8MN VHIP4 EvalBoard v1 and v2 reference design binding. This system exists in two generations, v1 and v2, which share a lot of commonality. The boards come with either single gigabit ethernet or an KSZ8794 fast-ethernet switch, boot from eMMC, and offer CAN interfaces via Microchip MCP25xx SPI CAN controllers, UART, and USB host. The GPU is not available in the SoC populated on these devices. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2026-01-17dt-bindings: vendor-prefixes: Document ifm electronic gmbhMarek Vasut
ifm is a manufacturer of industrial sensors, control technology and automation solutions. Document their vendor prefix, which is already used for ifm,ac14xx and other powerpc devices. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Marek Vasut <marex@nabladev.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2026-01-17dt-bindings: display: tegra: document Tegra30 VI and VIPSvyatoslav Ryhel
Existing Parallel VI interface schema for Tegra20 is fully compatible with Tegra30; hence, lets reuse it by setting fallback for Tegra30. Adjust existing VI schema to reflect that Tegra20 VI is compatible with Tegra30 by setting a fallback for Tegra30. Additionally, switch to using an enum instead of list of const. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-17dt-bindings: display: tegra: document Tegra132 MIPI calibration deviceSvyatoslav Ryhel
Document MIPI calibration device found in Tegra132. This compatible already exists in the Linux kernel, I have just documented it to satisfy warnings. Each Tegra SoC generation has unique set of registers which should be configured. They all differ, hence fallback is not suitable here. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-17dt-bindings: phy: mediatek,hdmi-phy: Document extra clocks for MT8195Nícolas F. R. A. Prado
MT8195's HDMI PHY block has 4 clocks instead of just a single one. Describe the extra clocks for it. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-3-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-01-17dt-bindings: phy: mediatek,hdmi-phy: Add support for MT8188 SoCLouis-Alexis Eyraud
Add compatible string for the HDMI PHY IP on MT8188 SoC, that is compatible with the one found on MT8195 SoC. Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-2-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-01-17dt-bindings: phy: mediatek,hdmi-phy: Fix clock output names for MT8195AngeloGioacchino Del Regno
For all of the HDMI PHYs compatible with the one found on MT8195 the output clock has a different datasheet name and specifically it is called "hdmi_txpll", differently from the older HDMI PHYs which output block is called "hdmitx_dig_cts". Replace clock output name string check by max item number one to allow the new name on all of the HDMI PHY IPs that are perfectly compatible with MT8195. [Louis-Alexis Eyraud: split patch, addressed previous feedback from mailing list, and reworded description] Fixes: c78fe548b062 ("dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20251217-mtk-genio-evk-hdmi-support-v2-1-a994976bb39a@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2026-01-16dt-bindings: can: renesas,rcar-canfd: Document RZ/T2H and RZ/N2H SoCsLad Prabhakar
Document the CAN-FD controller used on the RZ/T2H and RZ/N2H SoCs. The CAN-FD IP is largely compatible with the R-Car Gen4 block, but differs in that AFLPN and CFTML are different, there is no reset line for the IP, and it only supports two channels. Sync the resets and reset-names schema handling with other CAN-FD SoCs so DT validation stays consistent and maintainable. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260114154525.3169992-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2026-01-16dt-bindings: can: renesas,rcar-canfd: Document RZ/V2H(P) and RZ/V2N SoCsLad Prabhakar
Document CANFD IP found on the Renesas RZ/V2H(P) (R9A09G057) and RZ/V2N (R9A09G056) SoCs. The CANFD IP on these SoCs are identical to that found on the RZ/G3E (R9A09G047) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260114154525.3169992-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2026-01-16dt-bindings: can: renesas,rcar-canfd: Specify reset-namesLad Prabhakar
Specify the expected reset-names for the Renesas CAN-FD controller on RZ/G2L and RZ/G3E SoCs. The reset names rstp_n and rstc_n are defined in the SoC hardware manual and are already used by the driver since commit 76e9353a80e9 ("can: rcar_canfd: Add support for RZ/G2L family"). The reset-names property existed previously but was dropped by commit 466c8ef7b66b ("dt-bindings: can: renesas,rcar-canfd: Simplify the conditional schema"). Restore and constrain reset-names in the binding so DT schema checks match the actual hardware requirements and driver expectations. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260114154525.3169992-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2026-01-16dt-bindings: can: renesas,rcar-canfd: Document renesas,fd-only propertyBiju Das
The CANFD on RZ/{G2L,G3E} and R-Car Gen4 support 3 modes FD-Only mode, Classical CAN mode and CAN-FD mode. In FD-Only mode, communication in Classical CAN frame format is disabled. Document renesas,fd-only to handle this mode. As these SoCs support 3 modes, update the description of renesas,no-can-fd property and disallow it for R-Car Gen3. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20251126155911.320563-2-biju.das.jz@bp.renesas.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2026-01-16dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for KaanapaliJingyi Wang
Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm Kaanapali, which is compatible with X1E80100, use fallback to indicate this. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-16dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schemaCharan Pedumuru
Convert NVIDIA Tegra NAND Flash Controller binding to YAML format. Changes during Conversion: - Define new properties `power-domains` and `operating-points-v2` because the existing in tree DTS uses them. - Modify MAINTAINERS references to point the created YAML file. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-16dt-bindings: dma: Update ADMA bindings for tegra264sheetal
- Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal <sheetal@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-16Merge tag 'sound-6.19-rc6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound fixes from Takashi Iwai: "This became a bit larger than wished for, often seen as a bump at the middle, but almost all changes are small device-specific fixes, so the risk must be pretty low. - SoundWire fix for missing symbol export - Fixes for device-tree bindings - A fix for OOB access in USB-audio, spotted by fuzzer - Quirks for HD-audio, SoundWire, AMD ACP - A series of ASoC tlv320 and wsa codec fixes - Other misc fixes in PCM OSS error-handling, Cirrus scodec test, ASoC ops endianess, davinci, simple-card, and tegra" * tag 'sound-6.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (33 commits) ALSA: hda/tas2781: Add newly-released HP laptop ASoC: rt5640: Fix duplicate clock properties in DT binding ALSA: hda/realtek: Add quirk for HP Pavilion x360 to enable mute LED ASoC: tlv320adcx140: fix word length ASoC: tlv320adcx140: Propagate error codes during probe ASoC: tlv320adcx140: fix null pointer ASoC: tlv320adcx140: invert DRE_ENABLE ASoC: sdw_utils: cs42l43: Enable Headphone pin for LINEOUT jack type ASoC: sdw_utils: Call init callbacks on the correct codec DAI soundwire: Add missing EXPORT for sdw_slave_type ALSA: usb-audio: Prevent excessive number of frames ALSA: hda/cirrus_scodec_test: Fix test suite name ALSA: hda/cirrus_scodec_test: Fix incorrect setup of gpiochip ALSA: hda/realtek: Add quirk for Asus Zephyrus G14 2025 using CS35L56, fix speakers ASoC: amd: yc: Fix microphone on ASUS M6500RE ASoC: tegra: Revert fix for uninitialized flat cache warning in tegra210_ahub ASoC: dt-bindings: rockchip-spdif: Allow "port" node ASoC: dt-bindings: realtek,rt5640: Allow 7 for realtek,jack-detect-source ASoC: dt-bindings: realtek,rt5640: Add missing properties/node ASoC: dt-bindings: realtek,rt5640: Document port node ...
2026-01-16dt-bindings: serial: google,goldfish-tty: Convert to DT schemaKuan-Wei Chiu
Convert the Google Goldfish TTY binding to DT schema format. Move the file to the serial directory to match the subsystem. Update the example node name to 'serial' to comply with generic node naming standards. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260113092602.3197681-2-visitorckw@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-16dt-bindings: serial: sh-sci: Fold single-entry compatibles into enumLad Prabhakar
Group single compatibles into enum. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260112095722.25556-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-16dt-bindings: serial: renesas,rsci: Document RZ/V2H(P) and RZ/V2N SoCsLad Prabhakar
Document the serial communication interface (RSCI) used on the Renesas RZ/V2H(P) (R9A09G057) and RZ/V2N (R9A09G056) SoCs. These SoCs integrate the same RSCI IP block as the RZ/G3E (R9A09G047), so the RZ/G3E compatible is used as a fallback for both. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251222162909.155279-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-16dt-bindings: PCI: qcom: Document the Glymur PCIe ControllerPrudhvi Yarlagadda
On the Qualcomm Glymur platform the PCIe host is compatible with the DWC controller present on the X1E80100 platform. So document the PCIe controllers found on Glymur and use the X1E80100 compatible string as a fallback in the schema. Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250825-glymur_pcie5-v3-2-5c1d1730c16f@oss.qualcomm.com
2026-01-16dt-bindings: misc: google,android-pipe: Convert to DT schemaKuan-Wei Chiu
Convert the Android Goldfish QEMU Pipe binding to DT schema format. Move the file to the misc directory as it represents a miscellaneous communication device. Update the example node name to 'pipe' to comply with generic node naming standards and fix the mismatch between unit address and reg property in the original example. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260113092602.3197681-3-visitorckw@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-16Merge tag 'icc-6.19-rc6' of ↵Greg Kroah-Hartman
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-linus interconnect fixes for v6.19-rc This contains a few small fixes for the current cycle. - dt-bindings: interconnect: qcom,sa8775p-rpmh: Fix incorrectly added reg and clocks - MAINTAINERS: Add interconnect-clk.h to interconnect API entry - interconnect: debugfs: initialize src_node and dst_node to empty strings Signed-off-by: Georgi Djakov <djakov@kernel.org> * tag 'icc-6.19-rc6' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc: interconnect: debugfs: initialize src_node and dst_node to empty strings MAINTAINERS: Add interconnect-clk.h to interconnect API entry dt-bindings: interconnect: qcom,sa8775p-rpmh: Fix incorrectly added reg and clocks
2026-01-16dt-bindings: usb: Add binding for WCH CH334/CH335 hub controllerChaoyi Chen
The WCH CH334/CH335[0] are USB2.0 protocol compliant 4-port USB HUB controller chips, supporting USB2.0 high-speed and full-speed for upstream ports, and USB2.0 high-speed 480Mbps, full-speed 12Mbps and low-speed 1.5Mbps for downstream ports, supporting not only low-cost STT mode (single TT schedules 4 downstream ports in time share), but also supports high performance MTT mode (4 TTs each corresponding to 1 port, concurrent processing). Add a device tree binding for it. [0]: https://www.wch-ic.com/downloads/CH334DS1_PDF.html Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260113095827.115-2-kernel@airkyi.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2026-01-16dt-bindings: iommu: Add NVIDIA Tegra CMDQV supportAshish Mhetre
The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Restrict this property usage to Nvidia Tegra264 only. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-16dt-bindings: memory: tegra: Document DBB clock for Tegra264Thierry Reding
Accesses to external memory are routed through the data backbone (DBB) on Tegra264. A separate clock feeds this path and needs to be enabled whenever an IP block makes an access to external memory. The external memory controller driver is the best place to control this clock since it knows how many devices are actively accessing memory. Document the presence of this clock on Tegra264 only. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-16dt-bindings: tegra: pmc: Update aotag as an optional apertureJon Hunter
Not all Tegra SoCs or all versions of a particular Tegra SoC may include the AOTAG aperture. This change makes "aotag" as an optional aperture for Tegra234 and Tegra264. Co-developed-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-16dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibilityPierre-Henry Moussay
pic64gx has a clock controller compatible with mpfs-clkcfg. Don't permit the deprecated configuration that was never supported for this SoC. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260113-glue-justifier-566ffab2ffd3@spud Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-16dt-bindings: clock: mpfs-ccc: Add pic64gx compatibilityPierre-Henry Moussay
pic64gx SoC Clock Conditioning Circuitry is compatibles with the Polarfire SoC Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260113-guise-conceded-88030697b831@spud Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-15dt-bindings: net: airoha: npu: Add BA memory regionLorenzo Bianconi
Introduce Block Ack memory region used by NPU MT7996 (Eagle) offloading. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260108-airoha-ba-memory-region-v3-1-bf1814e5dcc4@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-15dt-bindings: net: adi,adin: document LP Termination propertyOsose Itua
Add "adi,low-cmode-impedance" boolean property which, when present, configures the PHY for the lowest common-mode impedance on the receive pair for 100BASE-TX operation by clearing the B_100_ZPTM_EN_DIMRX bit. This is suited for capacitive coupled applications and other applications where there may be a path for high common-mode noise to reach the PHY. If this value is not present, the value of the bit by default is 1, which is normal termination (zero-power termination) mode. Signed-off-by: Osose Itua <osose.itua@savoirfairelinux.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20260107221913.1334157-2-osose.itua@savoirfairelinux.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-15Merge tag 'phy_common_properties' of ↵Jakub Kicinski
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Vinod Koul says: ==================== phy common properties Introduce "rx-polarity" and "tx-polarity" device tree properties with Kunit tests (from Vladimir Oltean). * tag 'phy_common_properties' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: add phy_get_rx_polarity() and phy_get_tx_polarity() dt-bindings: phy-common-props: RX and TX lane polarity inversion dt-bindings: phy-common-props: ensure protocol-names are unique dt-bindings: phy-common-props: create a reusable "protocol-names" definition dt-bindings: phy: rename transmit-amplitude.yaml to phy-common-props.yaml ==================== Link: https://patch.msgid.link/aWeXvFcGNK5T6As9@vaman Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-15Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-6.19-rc6). No conflicts, or adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2026-01-15dt-bindings: net: wireless: ath11k: Combine two if:then: clausesKrzysztof Kozlowski
Simplify the binding by combining two if:then: clauses which have exactly the same conditional part. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251230114835.52504-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
2026-01-16Merge tag 'drm-misc-next-2026-01-15' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for 6.20: Core Changes: - atomic: Introduce Gamma/Degamma LUT size check - gem: Fix a leak in drm_gem_get_unmapped_area - gpuvm: API sanitation for Rust bindings - panic: Few corner-cases fixes Driver Changes: - Replace system workqueue with percpu equivalent - amdxdna: Update message buffer allocation requirements, Update firmware version check - imagination: Add AM62P support - ivpu: Implement warm boot flow - rockchip: Get rid of atomic_check fixups, Add Rockchip RK3506 Support - rocket: Cleanups - bridge: - dw-hdmi-qp: Add support for HPD-less setups - panel: - mantix: Various power management related improvements - new panels: Innolux G150XGE-L05, - dma-buf: - cma: Call clear_page instead of memset Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@redhat.com> Link: https://patch.msgid.link/20260115-lilac-dragon-of-opposition-ac0a30@houat
2026-01-15dt-bindings: display/msm/rgmu: Document A612 RGMUJie Zhang
RGMU a.k.a Reduced Graphics Management Unit is a small state machine with the sole purpose of providing IFPC (Inter Frame Power Collapse) support. Compared to GMU, it doesn't manage GPU clock, voltage scaling, bw voting or any other functionalities. All it does is detect an idle GPU and toggle the GDSC switch. As it doesn't access DDR space, it doesn't require iommu. So far, only Adreno 612 GPU has an RGMU core. Document it in qcom,adreno-rgmu.yaml. Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/696679/ Message-ID: <20251231-qcs615-spin-2-v6-4-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-01-15dt-bindings: display/msm: gpu: Document A612 GPUAkhil P Oommen
A612 GPU has a new IP called RGMU (Reduced Graphics Management Unit) which replaces GMU. But it doesn't do clock or voltage scaling. So we need the gpu core clock in the GPU node along with the power domain to do clock and voltage scaling from the kernel. Update the bindings to describe this GPU. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/696676/ Message-ID: <20251231-qcs615-spin-2-v6-3-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-01-15dt-bindings: display/msm: gpu: Simplify conditional schema logicAkhil P Oommen
JSON Schema conditionals can become complex and error-prone when combined with regex patterns. To improve readability and maintainability, replace nested if-else blocks with a flattened structure using explicit enums. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/696674/ Message-ID: <20251231-qcs615-spin-2-v6-2-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-01-15ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-namesAngeloGioacchino Del Regno
Both clocks and clock-names are missing (a lot of) entries: add all the used audio clocks and their description and also fix the example node. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: c861af7861aa ("ASoC: dt-bindings: mediatek: mt8192: re-add audio afe document") Link: https://patch.msgid.link/20260115125624.73598-3-angelogioacchino.delregno@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-13 07:28:39 +0000