diff options
Diffstat (limited to 'include/linux/mfd')
36 files changed, 2421 insertions, 272 deletions
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h deleted file mode 100644 index 172b2f201ae0..000000000000 --- a/include/linux/mfd/abx500/ab8500-gpio.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright ST-Ericsson 2010. - * - * Author: Bibek Basu <bibek.basu@stericsson.com> - * Licensed under GPLv2. - */ - -#ifndef _AB8500_GPIO_H -#define _AB8500_GPIO_H - -/* - * Platform data to register a block: only the initial gpio/irq number. - * Array sizes are large enough to contain all AB8500 and AB9540 GPIO - * registers. - */ - -struct abx500_gpio_platform_data { - int gpio_base; -}; - -enum abx500_gpio_pull_updown { - ABX500_GPIO_PULL_DOWN = 0x0, - ABX500_GPIO_PULL_NONE = 0x1, - ABX500_GPIO_PULL_UP = 0x3, -}; - -enum abx500_gpio_vinsel { - ABX500_GPIO_VINSEL_VBAT = 0x0, - ABX500_GPIO_VINSEL_VIN_1V8 = 0x1, - ABX500_GPIO_VINSEL_VDD_BIF = 0x2, -}; - -#endif /* _AB8500_GPIO_H */ diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index f4acd898dac9..4e7fe7417fc9 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h @@ -347,7 +347,6 @@ struct ab8500 { struct mutex lock; struct mutex irq_lock; atomic_t transfer_ongoing; - int irq_base; int irq; struct irq_domain *domain; enum ab8500_version version; @@ -368,7 +367,6 @@ struct ab8500 { }; struct ab8500_regulator_platform_data; -struct ab8500_gpio_platform_data; struct ab8500_codec_platform_data; struct ab8500_sysctrl_platform_data; @@ -379,10 +377,8 @@ struct ab8500_sysctrl_platform_data; * @regulator: machine-specific constraints for regulators */ struct ab8500_platform_data { - int irq_base; void (*init) (struct ab8500 *); struct ab8500_regulator_platform_data *regulator; - struct abx500_gpio_platform_data *gpio; struct ab8500_codec_platform_data *codec; struct ab8500_sysctrl_platform_data *sysctrl; }; diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index cb49417f8ba9..7b35c21170d5 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h @@ -139,6 +139,7 @@ #define ARIZONA_INPUT_ENABLES_STATUS 0x301 #define ARIZONA_INPUT_RATE 0x308 #define ARIZONA_INPUT_VOLUME_RAMP 0x309 +#define ARIZONA_HPF_CONTROL 0x30C #define ARIZONA_IN1L_CONTROL 0x310 #define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311 #define ARIZONA_DMIC1L_CONTROL 0x312 @@ -160,6 +161,7 @@ #define ARIZONA_IN4L_CONTROL 0x328 #define ARIZONA_ADC_DIGITAL_VOLUME_4L 0x329 #define ARIZONA_DMIC4L_CONTROL 0x32A +#define ARIZONA_IN4R_CONTROL 0x32C #define ARIZONA_ADC_DIGITAL_VOLUME_4R 0x32D #define ARIZONA_DMIC4R_CONTROL 0x32E #define ARIZONA_OUTPUT_ENABLES_1 0x400 @@ -224,6 +226,9 @@ #define ARIZONA_PDM_SPK1_CTRL_2 0x491 #define ARIZONA_PDM_SPK2_CTRL_1 0x492 #define ARIZONA_PDM_SPK2_CTRL_2 0x493 +#define ARIZONA_HP1_SHORT_CIRCUIT_CTRL 0x4A0 +#define ARIZONA_HP2_SHORT_CIRCUIT_CTRL 0x4A1 +#define ARIZONA_HP3_SHORT_CIRCUIT_CTRL 0x4A2 #define ARIZONA_SPK_CTRL_2 0x4B5 #define ARIZONA_SPK_CTRL_3 0x4B6 #define ARIZONA_DAC_COMP_1 0x4DC @@ -511,6 +516,38 @@ #define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D #define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E #define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F +#define ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE 0x750 +#define ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME 0x751 +#define ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE 0x752 +#define ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME 0x753 +#define ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE 0x754 +#define ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME 0x755 +#define ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE 0x756 +#define ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME 0x757 +#define ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE 0x758 +#define ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME 0x759 +#define ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE 0x75A +#define ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME 0x75B +#define ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE 0x75C +#define ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME 0x75D +#define ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE 0x75E +#define ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME 0x75F +#define ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE 0x760 +#define ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME 0x761 +#define ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE 0x762 +#define ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME 0x763 +#define ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE 0x764 +#define ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME 0x765 +#define ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE 0x766 +#define ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME 0x767 +#define ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE 0x768 +#define ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME 0x769 +#define ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE 0x76A +#define ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME 0x76B +#define ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE 0x76C +#define ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME 0x76D +#define ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE 0x76E +#define ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME 0x76F #define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780 #define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781 #define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782 @@ -997,6 +1034,27 @@ #define ARIZONA_DSP1_STATUS_1 0x1104 #define ARIZONA_DSP1_STATUS_2 0x1105 #define ARIZONA_DSP1_STATUS_3 0x1106 +#define ARIZONA_DSP1_STATUS_4 0x1107 +#define ARIZONA_DSP1_WDMA_BUFFER_1 0x1110 +#define ARIZONA_DSP1_WDMA_BUFFER_2 0x1111 +#define ARIZONA_DSP1_WDMA_BUFFER_3 0x1112 +#define ARIZONA_DSP1_WDMA_BUFFER_4 0x1113 +#define ARIZONA_DSP1_WDMA_BUFFER_5 0x1114 +#define ARIZONA_DSP1_WDMA_BUFFER_6 0x1115 +#define ARIZONA_DSP1_WDMA_BUFFER_7 0x1116 +#define ARIZONA_DSP1_WDMA_BUFFER_8 0x1117 +#define ARIZONA_DSP1_RDMA_BUFFER_1 0x1120 +#define ARIZONA_DSP1_RDMA_BUFFER_2 0x1121 +#define ARIZONA_DSP1_RDMA_BUFFER_3 0x1122 +#define ARIZONA_DSP1_RDMA_BUFFER_4 0x1123 +#define ARIZONA_DSP1_RDMA_BUFFER_5 0x1124 +#define ARIZONA_DSP1_RDMA_BUFFER_6 0x1125 +#define ARIZONA_DSP1_WDMA_CONFIG_1 0x1130 +#define ARIZONA_DSP1_WDMA_CONFIG_2 0x1131 +#define ARIZONA_DSP1_WDMA_OFFSET_1 0x1132 +#define ARIZONA_DSP1_RDMA_CONFIG_1 0x1134 +#define ARIZONA_DSP1_RDMA_OFFSET_1 0x1135 +#define ARIZONA_DSP1_EXTERNAL_START_SELECT_1 0x1138 #define ARIZONA_DSP1_SCRATCH_0 0x1140 #define ARIZONA_DSP1_SCRATCH_1 0x1141 #define ARIZONA_DSP1_SCRATCH_2 0x1142 @@ -1006,6 +1064,27 @@ #define ARIZONA_DSP2_STATUS_1 0x1204 #define ARIZONA_DSP2_STATUS_2 0x1205 #define ARIZONA_DSP2_STATUS_3 0x1206 +#define ARIZONA_DSP2_STATUS_4 0x1207 +#define ARIZONA_DSP2_WDMA_BUFFER_1 0x1210 +#define ARIZONA_DSP2_WDMA_BUFFER_2 0x1211 +#define ARIZONA_DSP2_WDMA_BUFFER_3 0x1212 +#define ARIZONA_DSP2_WDMA_BUFFER_4 0x1213 +#define ARIZONA_DSP2_WDMA_BUFFER_5 0x1214 +#define ARIZONA_DSP2_WDMA_BUFFER_6 0x1215 +#define ARIZONA_DSP2_WDMA_BUFFER_7 0x1216 +#define ARIZONA_DSP2_WDMA_BUFFER_8 0x1217 +#define ARIZONA_DSP2_RDMA_BUFFER_1 0x1220 +#define ARIZONA_DSP2_RDMA_BUFFER_2 0x1221 +#define ARIZONA_DSP2_RDMA_BUFFER_3 0x1222 +#define ARIZONA_DSP2_RDMA_BUFFER_4 0x1223 +#define ARIZONA_DSP2_RDMA_BUFFER_5 0x1224 +#define ARIZONA_DSP2_RDMA_BUFFER_6 0x1225 +#define ARIZONA_DSP2_WDMA_CONFIG_1 0x1230 +#define ARIZONA_DSP2_WDMA_CONFIG_2 0x1231 +#define ARIZONA_DSP2_WDMA_OFFSET_1 0x1232 +#define ARIZONA_DSP2_RDMA_CONFIG_1 0x1234 +#define ARIZONA_DSP2_RDMA_OFFSET_1 0x1235 +#define ARIZONA_DSP2_EXTERNAL_START_SELECT_1 0x1238 #define ARIZONA_DSP2_SCRATCH_0 0x1240 #define ARIZONA_DSP2_SCRATCH_1 0x1241 #define ARIZONA_DSP2_SCRATCH_2 0x1242 @@ -1015,6 +1094,27 @@ #define ARIZONA_DSP3_STATUS_1 0x1304 #define ARIZONA_DSP3_STATUS_2 0x1305 #define ARIZONA_DSP3_STATUS_3 0x1306 +#define ARIZONA_DSP3_STATUS_4 0x1307 +#define ARIZONA_DSP3_WDMA_BUFFER_1 0x1310 +#define ARIZONA_DSP3_WDMA_BUFFER_2 0x1311 +#define ARIZONA_DSP3_WDMA_BUFFER_3 0x1312 +#define ARIZONA_DSP3_WDMA_BUFFER_4 0x1313 +#define ARIZONA_DSP3_WDMA_BUFFER_5 0x1314 +#define ARIZONA_DSP3_WDMA_BUFFER_6 0x1315 +#define ARIZONA_DSP3_WDMA_BUFFER_7 0x1316 +#define ARIZONA_DSP3_WDMA_BUFFER_8 0x1317 +#define ARIZONA_DSP3_RDMA_BUFFER_1 0x1320 +#define ARIZONA_DSP3_RDMA_BUFFER_2 0x1321 +#define ARIZONA_DSP3_RDMA_BUFFER_3 0x1322 +#define ARIZONA_DSP3_RDMA_BUFFER_4 0x1323 +#define ARIZONA_DSP3_RDMA_BUFFER_5 0x1324 +#define ARIZONA_DSP3_RDMA_BUFFER_6 0x1325 +#define ARIZONA_DSP3_WDMA_CONFIG_1 0x1330 +#define ARIZONA_DSP3_WDMA_CONFIG_2 0x1331 +#define ARIZONA_DSP3_WDMA_OFFSET_1 0x1332 +#define ARIZONA_DSP3_RDMA_CONFIG_1 0x1334 +#define ARIZONA_DSP3_RDMA_OFFSET_1 0x1335 +#define ARIZONA_DSP3_EXTERNAL_START_SELECT_1 0x1338 #define ARIZONA_DSP3_SCRATCH_0 0x1340 #define ARIZONA_DSP3_SCRATCH_1 0x1341 #define ARIZONA_DSP3_SCRATCH_2 0x1342 @@ -1024,6 +1124,27 @@ #define ARIZONA_DSP4_STATUS_1 0x1404 #define ARIZONA_DSP4_STATUS_2 0x1405 #define ARIZONA_DSP4_STATUS_3 0x1406 +#define ARIZONA_DSP4_STATUS_4 0x1407 +#define ARIZONA_DSP4_WDMA_BUFFER_1 0x1410 +#define ARIZONA_DSP4_WDMA_BUFFER_2 0x1411 +#define ARIZONA_DSP4_WDMA_BUFFER_3 0x1412 +#define ARIZONA_DSP4_WDMA_BUFFER_4 0x1413 +#define ARIZONA_DSP4_WDMA_BUFFER_5 0x1414 +#define ARIZONA_DSP4_WDMA_BUFFER_6 0x1415 +#define ARIZONA_DSP4_WDMA_BUFFER_7 0x1416 +#define ARIZONA_DSP4_WDMA_BUFFER_8 0x1417 +#define ARIZONA_DSP4_RDMA_BUFFER_1 0x1420 +#define ARIZONA_DSP4_RDMA_BUFFER_2 0x1421 +#define ARIZONA_DSP4_RDMA_BUFFER_3 0x1422 +#define ARIZONA_DSP4_RDMA_BUFFER_4 0x1423 +#define ARIZONA_DSP4_RDMA_BUFFER_5 0x1424 +#define ARIZONA_DSP4_RDMA_BUFFER_6 0x1425 +#define ARIZONA_DSP4_WDMA_CONFIG_1 0x1430 +#define ARIZONA_DSP4_WDMA_CONFIG_2 0x1431 +#define ARIZONA_DSP4_WDMA_OFFSET_1 0x1432 +#define ARIZONA_DSP4_RDMA_CONFIG_1 0x1434 +#define ARIZONA_DSP4_RDMA_OFFSET_1 0x1435 +#define ARIZONA_DSP4_EXTERNAL_START_SELECT_1 0x1438 #define ARIZONA_DSP4_SCRATCH_0 0x1440 #define ARIZONA_DSP4_SCRATCH_1 0x1441 #define ARIZONA_DSP4_SCRATCH_2 0x1442 @@ -1665,9 +1786,9 @@ /* * R373 (0x175) - FLL1 Control 5 */ -#define ARIZONA_FLL1_FRATIO_MASK 0x0700 /* FLL1_FRATIO - [10:8] */ -#define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [10:8] */ -#define ARIZONA_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [10:8] */ +#define ARIZONA_FLL1_FRATIO_MASK 0x0F00 /* FLL1_FRATIO - [11:8] */ +#define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [11:8] */ +#define ARIZONA_FLL1_FRATIO_WIDTH 4 /* FLL1_FRATIO - [11:8] */ #define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */ #define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */ #define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */ @@ -2196,6 +2317,15 @@ /* * R677 (0x2A5) - Mic Detect 3 */ +#define ARIZONA_MICD_LVL_0 0x0004 /* MICD_LVL - [2] */ +#define ARIZONA_MICD_LVL_1 0x0008 /* MICD_LVL - [3] */ +#define ARIZONA_MICD_LVL_2 0x0010 /* MICD_LVL - [4] */ +#define ARIZONA_MICD_LVL_3 0x0020 /* MICD_LVL - [5] */ +#define ARIZONA_MICD_LVL_4 0x0040 /* MICD_LVL - [6] */ +#define ARIZONA_MICD_LVL_5 0x0080 /* MICD_LVL - [7] */ +#define ARIZONA_MICD_LVL_6 0x0100 /* MICD_LVL - [8] */ +#define ARIZONA_MICD_LVL_7 0x0200 /* MICD_LVL - [9] */ +#define ARIZONA_MICD_LVL_8 0x0400 /* MICD_LVL - [10] */ #define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ #define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ #define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ @@ -2293,8 +2423,18 @@ #define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ /* + * R780 (0x30C) - HPF Control + */ +#define ARIZONA_IN_HPF_CUT_MASK 0x0007 /* IN_HPF_CUT [2:0] */ +#define ARIZONA_IN_HPF_CUT_SHIFT 0 /* IN_HPF_CUT [2:0] */ +#define ARIZONA_IN_HPF_CUT_WIDTH 3 /* IN_HPF_CUT [2:0] */ + +/* * R784 (0x310) - IN1L Control */ +#define ARIZONA_IN1L_HPF_MASK 0x8000 /* IN1L_HPF - [15] */ +#define ARIZONA_IN1L_HPF_SHIFT 15 /* IN1L_HPF - [15] */ +#define ARIZONA_IN1L_HPF_WIDTH 1 /* IN1L_HPF - [15] */ #define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */ #define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */ #define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */ @@ -2333,6 +2473,9 @@ /* * R788 (0x314) - IN1R Control */ +#define ARIZONA_IN1R_HPF_MASK 0x8000 /* IN1R_HPF - [15] */ +#define ARIZONA_IN1R_HPF_SHIFT 15 /* IN1R_HPF - [15] */ +#define ARIZONA_IN1R_HPF_WIDTH 1 /* IN1R_HPF - [15] */ #define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ #define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ #define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ @@ -2362,6 +2505,9 @@ /* * R792 (0x318) - IN2L Control */ +#define ARIZONA_IN2L_HPF_MASK 0x8000 /* IN2L_HPF - [15] */ +#define ARIZONA_IN2L_HPF_SHIFT 15 /* IN2L_HPF - [15] */ +#define ARIZONA_IN2L_HPF_WIDTH 1 /* IN2L_HPF - [15] */ #define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */ #define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */ #define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */ @@ -2400,6 +2546,9 @@ /* * R796 (0x31C) - IN2R Control */ +#define ARIZONA_IN2R_HPF_MASK 0x8000 /* IN2R_HPF - [15] */ +#define ARIZONA_IN2R_HPF_SHIFT 15 /* IN2R_HPF - [15] */ +#define ARIZONA_IN2R_HPF_WIDTH 1 /* IN2R_HPF - [15] */ #define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ #define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ #define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ @@ -2429,6 +2578,9 @@ /* * R800 (0x320) - IN3L Control */ +#define ARIZONA_IN3L_HPF_MASK 0x8000 /* IN3L_HPF - [15] */ +#define ARIZONA_IN3L_HPF_SHIFT 15 /* IN3L_HPF - [15] */ +#define ARIZONA_IN3L_HPF_WIDTH 1 /* IN3L_HPF - [15] */ #define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */ #define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */ #define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */ @@ -2467,6 +2619,9 @@ /* * R804 (0x324) - IN3R Control */ +#define ARIZONA_IN3R_HPF_MASK 0x8000 /* IN3R_HPF - [15] */ +#define ARIZONA_IN3R_HPF_SHIFT 15 /* IN3R_HPF - [15] */ +#define ARIZONA_IN3R_HPF_WIDTH 1 /* IN3R_HPF - [15] */ #define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ #define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ #define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ @@ -2496,6 +2651,9 @@ /* * R808 (0x328) - IN4 Control */ +#define ARIZONA_IN4L_HPF_MASK 0x8000 /* IN4L_HPF - [15] */ +#define ARIZONA_IN4L_HPF_SHIFT 15 /* IN4L_HPF - [15] */ +#define ARIZONA_IN4L_HPF_WIDTH 1 /* IN4L_HPF - [15] */ #define ARIZONA_IN4_OSR_MASK 0x6000 /* IN4_OSR - [14:13] */ #define ARIZONA_IN4_OSR_SHIFT 13 /* IN4_OSR - [14:13] */ #define ARIZONA_IN4_OSR_WIDTH 2 /* IN4_OSR - [14:13] */ @@ -2526,6 +2684,13 @@ #define ARIZONA_IN4L_DMIC_DLY_WIDTH 6 /* IN4L_DMIC_DLY - [5:0] */ /* + * R812 (0x32C) - IN4R Control + */ +#define ARIZONA_IN4R_HPF_MASK 0x8000 /* IN4R_HPF - [15] */ +#define ARIZONA_IN4R_HPF_SHIFT 15 /* IN4R_HPF - [15] */ +#define ARIZONA_IN4R_HPF_WIDTH 1 /* IN4R_HPF - [15] */ + +/* * R813 (0x32D) - ADC Digital Volume 4R */ #define ARIZONA_IN_VU 0x0200 /* IN_VU */ @@ -3138,6 +3303,10 @@ /* * R1088 (0x440) - DRE Enable */ +#define ARIZONA_DRE3R_ENA 0x0020 /* DRE3R_ENA */ +#define ARIZONA_DRE3R_ENA_MASK 0x0020 /* DRE3R_ENA */ +#define ARIZONA_DRE3R_ENA_SHIFT 5 /* DRE3R_ENA */ +#define ARIZONA_DRE3R_ENA_WIDTH 1 /* DRE3R_ENA */ #define ARIZONA_DRE3L_ENA 0x0010 /* DRE3L_ENA */ #define ARIZONA_DRE3L_ENA_MASK 0x0010 /* DRE3L_ENA */ #define ARIZONA_DRE3L_ENA_SHIFT 4 /* DRE3L_ENA */ @@ -3260,6 +3429,30 @@ #define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ /* + * R1184 (0x4A0) - HP1 Short Circuit Ctrl + */ +#define ARIZONA_HP1_SC_ENA 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_MASK 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_SHIFT 12 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_WIDTH 1 /* HP1_SC_ENA */ + +/* + * R1185 (0x4A1) - HP2 Short Circuit Ctrl + */ +#define ARIZONA_HP2_SC_ENA 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_MASK 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_SHIFT 12 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_WIDTH 1 /* HP2_SC_ENA */ + +/* + * R1186 (0x4A2) - HP3 Short Circuit Ctrl + */ +#define ARIZONA_HP3_SC_ENA 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_MASK 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_SHIFT 12 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_WIDTH 1 /* HP3_SC_ENA */ + +/* * R1244 (0x4DC) - DAC comp 1 */ #define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */ @@ -3726,6 +3919,35 @@ #define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ /* + * R1355 (0x54B) - AIF2 Frame Ctrl 5 + */ +#define ARIZONA_AIF2TX3_SLOT_MASK 0x003F /* AIF2TX3_SLOT - [5:0] */ +#define ARIZONA_AIF2TX3_SLOT_SHIFT 0 /* AIF2TX3_SLOT - [5:0] */ +#define ARIZONA_AIF2TX3_SLOT_WIDTH 6 /* AIF2TX3_SLOT - [5:0] */ + +/* + * R1356 (0x54C) - AIF2 Frame Ctrl 6 + */ +#define ARIZONA_AIF2TX4_SLOT_MASK 0x003F /* AIF2TX4_SLOT - [5:0] */ +#define ARIZONA_AIF2TX4_SLOT_SHIFT 0 /* AIF2TX4_SLOT - [5:0] */ +#define ARIZONA_AIF2TX4_SLOT_WIDTH 6 /* AIF2TX4_SLOT - [5:0] */ + + +/* + * R1357 (0x54D) - AIF2 Frame Ctrl 7 + */ +#define ARIZONA_AIF2TX5_SLOT_MASK 0x003F /* AIF2TX5_SLOT - [5:0] */ +#define ARIZONA_AIF2TX5_SLOT_SHIFT 0 /* AIF2TX5_SLOT - [5:0] */ +#define ARIZONA_AIF2TX5_SLOT_WIDTH 6 /* AIF2TX5_SLOT - [5:0] */ + +/* + * R1358 (0x54E) - AIF2 Frame Ctrl 8 + */ +#define ARIZONA_AIF2TX6_SLOT_MASK 0x003F /* AIF2TX6_SLOT - [5:0] */ +#define ARIZONA_AIF2TX6_SLOT_SHIFT 0 /* AIF2TX6_SLOT - [5:0] */ +#define ARIZONA_AIF2TX6_SLOT_WIDTH 6 /* AIF2TX6_SLOT - [5:0] */ + +/* * R1361 (0x551) - AIF2 Frame Ctrl 11 */ #define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */ @@ -3740,8 +3962,52 @@ #define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ /* + * R1363 (0x553) - AIF2 Frame Ctrl 13 + */ +#define ARIZONA_AIF2RX3_SLOT_MASK 0x003F /* AIF2RX3_SLOT - [5:0] */ +#define ARIZONA_AIF2RX3_SLOT_SHIFT 0 /* AIF2RX3_SLOT - [5:0] */ +#define ARIZONA_AIF2RX3_SLOT_WIDTH 6 /* AIF2RX3_SLOT - [5:0] */ + +/* + * R1364 (0x554) - AIF2 Frame Ctrl 14 + */ +#define ARIZONA_AIF2RX4_SLOT_MASK 0x003F /* AIF2RX4_SLOT - [5:0] */ +#define ARIZONA_AIF2RX4_SLOT_SHIFT 0 /* AIF2RX4_SLOT - [5:0] */ +#define ARIZONA_AIF2RX4_SLOT_WIDTH 6 /* AIF2RX4_SLOT - [5:0] */ + +/* + * R1365 (0x555) - AIF2 Frame Ctrl 15 + */ +#define ARIZONA_AIF2RX5_SLOT_MASK 0x003F /* AIF2RX5_SLOT - [5:0] */ +#define ARIZONA_AIF2RX5_SLOT_SHIFT 0 /* AIF2RX5_SLOT - [5:0] */ +#define ARIZONA_AIF2RX5_SLOT_WIDTH 6 /* AIF2RX5_SLOT - [5:0] */ + +/* + * R1366 (0x556) - AIF2 Frame Ctrl 16 + */ +#define ARIZONA_AIF2RX6_SLOT_MASK 0x003F /* AIF2RX6_SLOT - [5:0] */ +#define ARIZONA_AIF2RX6_SLOT_SHIFT 0 /* AIF2RX6_SLOT - [5:0] */ +#define ARIZONA_AIF2RX6_SLOT_WIDTH 6 /* AIF2RX6_SLOT - [5:0] */ + +/* * R1369 (0x559) - AIF2 Tx Enables */ +#define ARIZONA_AIF2TX6_ENA 0x0020 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_MASK 0x0020 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_SHIFT 5 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_WIDTH 1 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX5_ENA 0x0010 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_MASK 0x0010 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_SHIFT 4 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_WIDTH 1 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX4_ENA 0x0008 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_MASK 0x0008 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_SHIFT 3 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_WIDTH 1 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX3_ENA 0x0004 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_MASK 0x0004 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_SHIFT 2 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_WIDTH 1 /* AIF2TX3_ENA */ #define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ #define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ #define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ @@ -3754,6 +4020,22 @@ /* * R1370 (0x55A) - AIF2 Rx Enables */ +#define ARIZONA_AIF2RX6_ENA 0x0020 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_MASK 0x0020 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_SHIFT 5 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_WIDTH 1 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX5_ENA 0x0010 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_MASK 0x0010 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_SHIFT 4 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_WIDTH 1 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX4_ENA 0x0008 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_MASK 0x0008 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_SHIFT 3 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_WIDTH 1 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX3_ENA 0x0004 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_MASK 0x0004 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_SHIFT 2 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_WIDTH 1 /* AIF2RX3_ENA */ #define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ #define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ #define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ diff --git a/include/linux/mfd/as3722.h b/include/linux/mfd/as3722.h index 16bf8a0dcd97..8d43e9f2a842 100644 --- a/include/linux/mfd/as3722.h +++ b/include/linux/mfd/as3722.h @@ -151,6 +151,7 @@ #define AS3722_ASIC_ID1_REG 0x90 #define AS3722_ASIC_ID2_REG 0x91 #define AS3722_LOCK_REG 0x9E +#define AS3722_FUSE7_REG 0xA7 #define AS3722_MAX_REGISTER 0xF4 #define AS3722_SD0_EXT_ENABLE_MASK 0x03 @@ -224,6 +225,7 @@ #define AS3722_SD_VSEL_MASK 0x7F #define AS3722_SD0_VSEL_MIN 0x01 #define AS3722_SD0_VSEL_MAX 0x5A +#define AS3722_SD0_VSEL_LOW_VOL_MAX 0x6E #define AS3722_SD2_VSEL_MIN 0x01 #define AS3722_SD2_VSEL_MAX 0x7F @@ -314,6 +316,7 @@ #define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3) #define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4) #define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5) +#define AS3722_GPIO_IOSF_SD0_OUT AS3722_GPIO_IOSF_VAL(6) #define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7) #define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8) #define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9) @@ -341,6 +344,8 @@ #define AS3722_EXT_CONTROL_ENABLE2 0x2 #define AS3722_EXT_CONTROL_ENABLE3 0x3 +#define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4) + /* Interrupt IDs */ enum as3722_irq { AS3722_IRQ_LID, diff --git a/include/linux/mfd/bcm590xx.h b/include/linux/mfd/bcm590xx.h new file mode 100644 index 000000000000..434df2d4e587 --- /dev/null +++ b/include/linux/mfd/bcm590xx.h @@ -0,0 +1,31 @@ +/* + * Broadcom BCM590xx PMU + * + * Copyright 2014 Linaro Limited + * Author: Matt Porter <mporter@linaro.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_BCM590XX_H +#define __LINUX_MFD_BCM590XX_H + +#include <linux/device.h> +#include <linux/i2c.h> +#include <linux/regmap.h> + +/* max register address */ +#define BCM590XX_MAX_REGISTER 0xe7 + +struct bcm590xx { + struct device *dev; + struct i2c_client *i2c_client; + struct regmap *regmap; + unsigned int id; +}; + +#endif /* __LINUX_MFD_BCM590XX_H */ diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h index 21e21b81cc75..bba65f51a0b5 100644 --- a/include/linux/mfd/da9052/da9052.h +++ b/include/linux/mfd/da9052/da9052.h @@ -83,6 +83,7 @@ enum da9052_chip_id { DA9053_AA, DA9053_BA, DA9053_BB, + DA9053_BC, }; struct da9052_pdata; diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h index 2d2a0af675fd..00a9aac5d1e8 100644 --- a/include/linux/mfd/da9063/core.h +++ b/include/linux/mfd/da9063/core.h @@ -33,6 +33,10 @@ enum da9063_models { PMIC_DA9063 = 0x61, }; +enum da9063_variant_codes { + PMIC_DA9063_BB = 0x5 +}; + /* Interrupts */ enum da9063_irqs { DA9063_IRQ_ONKEY = 0, @@ -72,7 +76,7 @@ struct da9063 { /* Device */ struct device *dev; unsigned short model; - unsigned short revision; + unsigned char variant_code; unsigned int flags; /* Control interface */ diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h index 5834813fb5f3..09a85c699da1 100644 --- a/include/linux/mfd/da9063/registers.h +++ b/include/linux/mfd/da9063/registers.h @@ -17,11 +17,7 @@ #define _DA9063_REG_H #define DA9063_I2C_PAGE_SEL_SHIFT 1 - #define DA9063_EVENT_REG_NUM 4 -#define DA9210_EVENT_REG_NUM 2 -#define DA9063_EXT_EVENT_REG_NUM (DA9063_EVENT_REG_NUM + \ - DA9210_EVENT_REG_NUM) /* Page selection I2C or SPI always in the begining of any page. */ /* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */ @@ -61,9 +57,9 @@ #define DA9063_REG_GPIO_10_11 0x1A #define DA9063_REG_GPIO_12_13 0x1B #define DA9063_REG_GPIO_14_15 0x1C -#define DA9063_REG_GPIO_MODE_0_7 0x1D -#define DA9063_REG_GPIO_MODE_8_15 0x1E -#define DA9063_REG_GPIO_SWITCH_CONT 0x1F +#define DA9063_REG_GPIO_MODE0_7 0x1D +#define DA9063_REG_GPIO_MODE8_15 0x1E +#define DA9063_REG_SWITCH_CONT 0x1F /* Regulator Control Registers */ #define DA9063_REG_BCORE2_CONT 0x20 @@ -83,7 +79,7 @@ #define DA9063_REG_LDO9_CONT 0x2E #define DA9063_REG_LDO10_CONT 0x2F #define DA9063_REG_LDO11_CONT 0x30 -#define DA9063_REG_VIB 0x31 +#define DA9063_REG_SUPPLIES 0x31 #define DA9063_REG_DVC_1 0x32 #define DA9063_REG_DVC_2 0x33 @@ -97,9 +93,9 @@ #define DA9063_REG_ADCIN1_RES 0x3A #define DA9063_REG_ADCIN2_RES 0x3B #define DA9063_REG_ADCIN3_RES 0x3C -#define DA9063_REG_MON1_RES 0x3D -#define DA9063_REG_MON2_RES 0x3E -#define DA9063_REG_MON3_RES 0x3F +#define DA9063_REG_MON_A8_RES 0x3D +#define DA9063_REG_MON_A9_RES 0x3E +#define DA9063_REG_MON_A10_RES 0x3F /* RTC Calendar and Alarm Registers */ #define DA9063_REG_COUNT_S 0x40 @@ -108,15 +104,16 @@ #define DA9063_REG_COUNT_D 0x43 #define DA9063_REG_COUNT_MO 0x44 #define DA9063_REG_COUNT_Y 0x45 -#define DA9063_REG_ALARM_MI 0x46 -#define DA9063_REG_ALARM_H 0x47 -#define DA9063_REG_ALARM_D 0x48 -#define DA9063_REG_ALARM_MO 0x49 -#define DA9063_REG_ALARM_Y 0x4A -#define DA9063_REG_SECOND_A 0x4B -#define DA9063_REG_SECOND_B 0x4C -#define DA9063_REG_SECOND_C 0x4D -#define DA9063_REG_SECOND_D 0x4E +#define DA9063_REG_ALARM_S 0x46 +#define DA9063_REG_ALARM_MI 0x47 +#define DA9063_REG_ALARM_H 0x48 +#define DA9063_REG_ALARM_D 0x49 +#define DA9063_REG_ALARM_MO 0x4A +#define DA9063_REG_ALARM_Y 0x4B +#define DA9063_REG_SECOND_A 0x4C +#define DA9063_REG_SECOND_B 0x4D +#define DA9063_REG_SECOND_C 0x4E +#define DA9063_REG_SECOND_D 0x4F /* Sequencer Control Registers */ #define DA9063_REG_SEQ 0x81 @@ -226,35 +223,37 @@ #define DA9063_REG_CONFIG_J 0x10F #define DA9063_REG_CONFIG_K 0x110 #define DA9063_REG_CONFIG_L 0x111 -#define DA9063_REG_MON_REG_1 0x112 -#define DA9063_REG_MON_REG_2 0x113 -#define DA9063_REG_MON_REG_3 0x114 -#define DA9063_REG_MON_REG_4 0x115 -#define DA9063_REG_MON_REG_5 0x116 -#define DA9063_REG_MON_REG_6 0x117 -#define DA9063_REG_TRIM_CLDR 0x118 - +#define DA9063_REG_CONFIG_M 0x112 +#define DA9063_REG_CONFIG_N 0x113 + +#define DA9063_REG_MON_REG_1 0x114 +#define DA9063_REG_MON_REG_2 0x115 +#define DA9063_REG_MON_REG_3 0x116 +#define DA9063_REG_MON_REG_4 0x117 +#define DA9063_REG_MON_REG_5 0x11E +#define DA9063_REG_MON_REG_6 0x11F +#define DA9063_REG_TRIM_CLDR 0x120 /* General Purpose Registers */ -#define DA9063_REG_GP_ID_0 0x119 -#define DA9063_REG_GP_ID_1 0x11A -#define DA9063_REG_GP_ID_2 0x11B -#define DA9063_REG_GP_ID_3 0x11C -#define DA9063_REG_GP_ID_4 0x11D -#define DA9063_REG_GP_ID_5 0x11E -#define DA9063_REG_GP_ID_6 0x11F -#define DA9063_REG_GP_ID_7 0x120 -#define DA9063_REG_GP_ID_8 0x121 -#define DA9063_REG_GP_ID_9 0x122 -#define DA9063_REG_GP_ID_10 0x123 -#define DA9063_REG_GP_ID_11 0x124 -#define DA9063_REG_GP_ID_12 0x125 -#define DA9063_REG_GP_ID_13 0x126 -#define DA9063_REG_GP_ID_14 0x127 -#define DA9063_REG_GP_ID_15 0x128 -#define DA9063_REG_GP_ID_16 0x129 -#define DA9063_REG_GP_ID_17 0x12A -#define DA9063_REG_GP_ID_18 0x12B -#define DA9063_REG_GP_ID_19 0x12C +#define DA9063_REG_GP_ID_0 0x121 +#define DA9063_REG_GP_ID_1 0x122 +#define DA9063_REG_GP_ID_2 0x123 +#define DA9063_REG_GP_ID_3 0x124 +#define DA9063_REG_GP_ID_4 0x125 +#define DA9063_REG_GP_ID_5 0x126 +#define DA9063_REG_GP_ID_6 0x127 +#define DA9063_REG_GP_ID_7 0x128 +#define DA9063_REG_GP_ID_8 0x129 +#define DA9063_REG_GP_ID_9 0x12A +#define DA9063_REG_GP_ID_10 0x12B +#define DA9063_REG_GP_ID_11 0x12C +#define DA9063_REG_GP_ID_12 0x12D +#define DA9063_REG_GP_ID_13 0x12E +#define DA9063_REG_GP_ID_14 0x12F +#define DA9063_REG_GP_ID_15 0x130 +#define DA9063_REG_GP_ID_16 0x131 +#define DA9063_REG_GP_ID_17 0x132 +#define DA9063_REG_GP_ID_18 0x133 +#define DA9063_REG_GP_ID_19 0x134 /* Chip ID and variant */ #define DA9063_REG_CHIP_ID 0x181 @@ -405,8 +404,10 @@ /* DA9063_REG_CONTROL_B (addr=0x0F) */ #define DA9063_CHG_SEL 0x01 #define DA9063_WATCHDOG_PD 0x02 +#define DA9063_RESET_BLINKING 0x04 #define DA9063_NRES_MODE 0x08 #define DA9063_NONKEY_LOCK 0x10 +#define DA9063_BUCK_SLOWSTART 0x80 /* DA9063_REG_CONTROL_C (addr=0x10) */ #define DA9063_DEBOUNCING_MASK 0x07 @@ -466,6 +467,7 @@ #define DA9063_GPADC_PAUSE 0x02 #define DA9063_PMIF_DIS 0x04 #define DA9063_HS2WIRE_DIS 0x08 +#define DA9063_CLDR_PAUSE 0x10 #define DA9063_BBAT_DIS 0x20 #define DA9063_OUT_32K_PAUSE 0x40 #define DA9063_PMCONT_DIS 0x80 @@ -660,7 +662,7 @@ #define DA9063_GPIO15_TYPE_GPO 0x04 #define DA9063_GPIO15_NO_WAKEUP 0x80 -/* DA9063_REG_GPIO_MODE_0_7 (addr=0x1D) */ +/* DA9063_REG_GPIO_MODE0_7 (addr=0x1D) */ #define DA9063_GPIO0_MODE 0x01 #define DA9063_GPIO1_MODE 0x02 #define DA9063_GPIO2_MODE 0x04 @@ -670,7 +672,7 @@ #define DA9063_GPIO6_MODE 0x40 #define DA9063_GPIO7_MODE 0x80 -/* DA9063_REG_GPIO_MODE_8_15 (addr=0x1E) */ +/* DA9063_REG_GPIO_MODE8_15 (addr=0x1E) */ #define DA9063_GPIO8_MODE 0x01 #define DA9063_GPIO9_MODE 0x02 #define DA9063_GPIO10_MODE 0x04 @@ -702,12 +704,12 @@ #define DA9063_SWITCH_SR_5MV 0x10 #define DA9063_SWITCH_SR_10MV 0x20 #define DA9063_SWITCH_SR_50MV 0x30 -#define DA9063_SWITCH_SR_DIS 0x40 +#define DA9063_CORE_SW_INTERNAL 0x40 #define DA9063_CP_EN_MODE 0x80 /* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */ #define DA9063_BUCK_EN 0x01 -#define DA9063_BUCK_GPI_MASK 0x06 +#define DA9063_BUCK_GPI_MASK 0x06 #define DA9063_BUCK_GPI_OFF 0x00 #define DA9063_BUCK_GPI_GPIO1 0x02 #define DA9063_BUCK_GPI_GPIO2 0x04 @@ -841,25 +843,27 @@ #define DA9063_COUNT_YEAR_MASK 0x3F #define DA9063_MONITOR 0x40 -/* DA9063_REG_ALARM_MI (addr=0x46) */ +/* DA9063_REG_ALARM_S (addr=0x46) */ +#define DA9063_ALARM_S_MASK 0x3F #define DA9063_ALARM_STATUS_ALARM 0x80 #define DA9063_ALARM_STATUS_TICK 0x40 +/* DA9063_REG_ALARM_MI (addr=0x47) */ #define DA9063_ALARM_MIN_MASK 0x3F -/* DA9063_REG_ALARM_H (addr=0x47) */ +/* DA9063_REG_ALARM_H (addr=0x48) */ #define DA9063_ALARM_HOUR_MASK 0x1F -/* DA9063_REG_ALARM_D (addr=0x48) */ +/* DA9063_REG_ALARM_D (addr=0x49) */ #define DA9063_ALARM_DAY_MASK 0x1F -/* DA9063_REG_ALARM_MO (addr=0x49) */ +/* DA9063_REG_ALARM_MO (addr=0x4A) */ #define DA9063_TICK_WAKE 0x20 #define DA9063_TICK_TYPE 0x10 #define DA9063_TICK_TYPE_SEC 0x00 #define DA9063_TICK_TYPE_MIN 0x10 #define DA9063_ALARM_MONTH_MASK 0x0F -/* DA9063_REG_ALARM_Y (addr=0x4A) */ +/* DA9063_REG_ALARM_Y (addr=0x4B) */ #define DA9063_TICK_ON 0x80 #define DA9063_ALARM_ON 0x40 #define DA9063_ALARM_YEAR_MASK 0x3F @@ -906,7 +910,7 @@ /* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */ #define DA9063_BUCK_FB_MASK 0x07 -#define DA9063_BUCK_PD_DIS_SHIFT 5 +#define DA9063_BUCK_PD_DIS_MASK 0x20 #define DA9063_BUCK_MODE_MASK 0xC0 #define DA9063_BUCK_MODE_MANUAL 0x00 #define DA9063_BUCK_MODE_SLEEP 0x40 diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index 060e11256fbc..bf5109d38a26 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -183,8 +183,6 @@ struct prcmu_pdata bool enable_set_ddr_opp; bool enable_ape_opp_100_voltage; struct ab8500_platform_data *ab_platdata; - int ab_irq; - int irq_base; u32 version_offset; u32 legacy_offset; u32 adt_offset; diff --git a/include/linux/mfd/lp3943.h b/include/linux/mfd/lp3943.h new file mode 100644 index 000000000000..3490db782988 --- /dev/null +++ b/include/linux/mfd/lp3943.h @@ -0,0 +1,114 @@ +/* + * TI/National Semiconductor LP3943 Device + * + * Copyright 2013 Texas Instruments + * + * Author: Milo Kim <milo.kim@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __MFD_LP3943_H__ +#define __MFD_LP3943_H__ + +#include <linux/gpio.h> +#include <linux/pwm.h> +#include <linux/regmap.h> + +/* Registers */ +#define LP3943_REG_GPIO_A 0x00 +#define LP3943_REG_GPIO_B 0x01 +#define LP3943_REG_PRESCALE0 0x02 +#define LP3943_REG_PWM0 0x03 +#define LP3943_REG_PRESCALE1 0x04 +#define LP3943_REG_PWM1 0x05 +#define LP3943_REG_MUX0 0x06 +#define LP3943_REG_MUX1 0x07 +#define LP3943_REG_MUX2 0x08 +#define LP3943_REG_MUX3 0x09 + +/* Bit description for LP3943_REG_MUX0 ~ 3 */ +#define LP3943_GPIO_IN 0x00 +#define LP3943_GPIO_OUT_HIGH 0x00 +#define LP3943_GPIO_OUT_LOW 0x01 +#define LP3943_DIM_PWM0 0x02 +#define LP3943_DIM_PWM1 0x03 + +#define LP3943_NUM_PWMS 2 + +enum lp3943_pwm_output { + LP3943_PWM_OUT0, + LP3943_PWM_OUT1, + LP3943_PWM_OUT2, + LP3943_PWM_OUT3, + LP3943_PWM_OUT4, + LP3943_PWM_OUT5, + LP3943_PWM_OUT6, + LP3943_PWM_OUT7, + LP3943_PWM_OUT8, + LP3943_PWM_OUT9, + LP3943_PWM_OUT10, + LP3943_PWM_OUT11, + LP3943_PWM_OUT12, + LP3943_PWM_OUT13, + LP3943_PWM_OUT14, + LP3943_PWM_OUT15, +}; + +/* + * struct lp3943_pwm_map + * @output: Output pins which are mapped to each PWM channel + * @num_outputs: Number of outputs + */ +struct lp3943_pwm_map { + enum lp3943_pwm_output *output; + int num_outputs; +}; + +/* + * struct lp3943_platform_data + * @pwms: Output channel definitions for PWM channel 0 and 1 + */ +struct lp3943_platform_data { + struct lp3943_pwm_map *pwms[LP3943_NUM_PWMS]; +}; + +/* + * struct lp3943_reg_cfg + * @reg: Register address + * @mask: Register bit mask to be updated + * @shift: Register bit shift + */ +struct lp3943_reg_cfg { + u8 reg; + u8 mask; + u8 shift; +}; + +/* + * struct lp3943 + * @dev: Parent device pointer + * @regmap: Used for I2C communication on accessing registers + * @pdata: LP3943 platform specific data + * @mux_cfg: Register configuration for pin MUX + * @pin_used: Bit mask for output pin used. + * This bitmask is used for pin assignment management. + * 1 = pin used, 0 = available. + * Only LSB 16 bits are used, but it is unsigned long type + * for atomic bitwise operations. + */ +struct lp3943 { + struct device *dev; + struct regmap *regmap; + struct lp3943_platform_data *pdata; + const struct lp3943_reg_cfg *mux_cfg; + unsigned long pin_used; +}; + +int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read); +int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data); +int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data); +#endif diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h index 3e1df644c407..8feac782fa83 100644 --- a/include/linux/mfd/lpc_ich.h +++ b/include/linux/mfd/lpc_ich.h @@ -21,23 +21,26 @@ #define LPC_ICH_H /* Watchdog resources */ -#define ICH_RES_IO_TCO 0 -#define ICH_RES_IO_SMI 1 -#define ICH_RES_MEM_OFF 2 -#define ICH_RES_MEM_GCS 0 +#define ICH_RES_IO_TCO 0 +#define ICH_RES_IO_SMI 1 +#define ICH_RES_MEM_OFF 2 +#define ICH_RES_MEM_GCS_PMC 0 /* GPIO resources */ #define ICH_RES_GPIO 0 #define ICH_RES_GPE0 1 /* GPIO compatibility */ -#define ICH_I3100_GPIO 0x401 -#define ICH_V5_GPIO 0x501 -#define ICH_V6_GPIO 0x601 -#define ICH_V7_GPIO 0x701 -#define ICH_V9_GPIO 0x801 -#define ICH_V10CORP_GPIO 0xa01 -#define ICH_V10CONS_GPIO 0xa11 +enum { + ICH_I3100_GPIO, + ICH_V5_GPIO, + ICH_V6_GPIO, + ICH_V7_GPIO, + ICH_V9_GPIO, + ICH_V10CORP_GPIO, + ICH_V10CONS_GPIO, + AVOTON_GPIO, +}; struct lpc_ich_info { char name[32]; diff --git a/include/linux/mfd/max14577-private.h b/include/linux/mfd/max14577-private.h new file mode 100644 index 000000000000..c9b332fb0d5d --- /dev/null +++ b/include/linux/mfd/max14577-private.h @@ -0,0 +1,322 @@ +/* + * max14577-private.h - Common API for the Maxim 14577 internal sub chip + * + * Copyright (C) 2013 Samsung Electrnoics + * Chanwoo Choi <cw00.choi@samsung.com> + * Krzysztof Kozlowski <k.kozlowski@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAX14577_PRIVATE_H__ +#define __MAX14577_PRIVATE_H__ + +#include <linux/i2c.h> +#include <linux/regmap.h> + +#define MAX14577_REG_INVALID (0xff) + +/* Slave addr = 0x4A: Interrupt */ +enum max14577_reg { + MAX14577_REG_DEVICEID = 0x00, + MAX14577_REG_INT1 = 0x01, + MAX14577_REG_INT2 = 0x02, + MAX14577_REG_INT3 = 0x03, + MAX14577_REG_STATUS1 = 0x04, + MAX14577_REG_STATUS2 = 0x05, + MAX14577_REG_STATUS3 = 0x06, + MAX14577_REG_INTMASK1 = 0x07, + MAX14577_REG_INTMASK2 = 0x08, + MAX14577_REG_INTMASK3 = 0x09, + MAX14577_REG_CDETCTRL1 = 0x0A, + MAX14577_REG_RFU = 0x0B, + MAX14577_REG_CONTROL1 = 0x0C, + MAX14577_REG_CONTROL2 = 0x0D, + MAX14577_REG_CONTROL3 = 0x0E, + MAX14577_REG_CHGCTRL1 = 0x0F, + MAX14577_REG_CHGCTRL2 = 0x10, + MAX14577_REG_CHGCTRL3 = 0x11, + MAX14577_REG_CHGCTRL4 = 0x12, + MAX14577_REG_CHGCTRL5 = 0x13, + MAX14577_REG_CHGCTRL6 = 0x14, + MAX14577_REG_CHGCTRL7 = 0x15, + + MAX14577_REG_END, +}; + +/* Slave addr = 0x4A: MUIC */ +enum max14577_muic_reg { + MAX14577_MUIC_REG_STATUS1 = 0x04, + MAX14577_MUIC_REG_STATUS2 = 0x05, + MAX14577_MUIC_REG_CONTROL1 = 0x0C, + MAX14577_MUIC_REG_CONTROL3 = 0x0E, + + MAX14577_MUIC_REG_END, +}; + +enum max14577_muic_charger_type { + MAX14577_CHARGER_TYPE_NONE = 0, + MAX14577_CHARGER_TYPE_USB, + MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT, + MAX14577_CHARGER_TYPE_DEDICATED_CHG, + MAX14577_CHARGER_TYPE_SPECIAL_500MA, + MAX14577_CHARGER_TYPE_SPECIAL_1A, + MAX14577_CHARGER_TYPE_RESERVED, + MAX14577_CHARGER_TYPE_DEAD_BATTERY = 7, +}; + +/* MAX14577 interrupts */ +#define INT1_ADC_MASK (0x1 << 0) +#define INT1_ADCLOW_MASK (0x1 << 1) +#define INT1_ADCERR_MASK (0x1 << 2) + +#define INT2_CHGTYP_MASK (0x1 << 0) +#define INT2_CHGDETRUN_MASK (0x1 << 1) +#define INT2_DCDTMR_MASK (0x1 << 2) +#define INT2_DBCHG_MASK (0x1 << 3) +#define INT2_VBVOLT_MASK (0x1 << 4) + +#define INT3_EOC_MASK (0x1 << 0) +#define INT3_CGMBC_MASK (0x1 << 1) +#define INT3_OVP_MASK (0x1 << 2) +#define INT3_MBCCHGERR_MASK (0x1 << 3) + +/* MAX14577 DEVICE ID register */ +#define DEVID_VENDORID_SHIFT 0 +#define DEVID_DEVICEID_SHIFT 3 +#define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT) +#define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT) + +/* MAX14577 STATUS1 register */ +#define STATUS1_ADC_SHIFT 0 +#define STATUS1_ADCLOW_SHIFT 5 +#define STATUS1_ADCERR_SHIFT 6 +#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT) +#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT) +#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT) + +/* MAX14577 STATUS2 register */ +#define STATUS2_CHGTYP_SHIFT 0 +#define STATUS2_CHGDETRUN_SHIFT 3 +#define STATUS2_DCDTMR_SHIFT 4 +#define STATUS2_DBCHG_SHIFT 5 +#define STATUS2_VBVOLT_SHIFT 6 +#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT) +#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT) +#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT) +#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT) +#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT) + +/* MAX14577 CONTROL1 register */ +#define COMN1SW_SHIFT 0 +#define COMP2SW_SHIFT 3 +#define MICEN_SHIFT 6 +#define IDBEN_SHIFT 7 +#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT) +#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT) +#define MICEN_MASK (0x1 << MICEN_SHIFT) +#define IDBEN_MASK (0x1 << IDBEN_SHIFT) +#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK) +#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \ + | (1 << COMN1SW_SHIFT)) +#define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ + | (2 << COMN1SW_SHIFT)) +#define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \ + | (3 << COMN1SW_SHIFT)) +#define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ + | (0 << COMN1SW_SHIFT)) + +/* MAX14577 CONTROL2 register */ +#define CTRL2_LOWPWR_SHIFT (0) +#define CTRL2_ADCEN_SHIFT (1) +#define CTRL2_CPEN_SHIFT (2) +#define CTRL2_SFOUTASRT_SHIFT (3) +#define CTRL2_SFOUTORD_SHIFT (4) +#define CTRL2_ACCDET_SHIFT (5) +#define CTRL2_USBCPINT_SHIFT (6) +#define CTRL2_RCPS_SHIFT (7) +#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT) +#define CTRL2_ADCEN_MASK (0x1 << CTRL2_ADCEN_SHIFT) +#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT) +#define CTRL2_SFOUTASRT_MASK (0x1 << CTRL2_SFOUTASRT_SHIFT) +#define CTRL2_SFOUTORD_MASK (0x1 << CTRL2_SFOUTORD_SHIFT) +#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT) +#define CTRL2_USBCPINT_MASK (0x1 << CTRL2_USBCPINT_SHIFT) +#define CTRL2_RCPS_MASK (0x1 << CTR2_RCPS_SHIFT) + +#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \ + (0 << CTRL2_LOWPWR_SHIFT)) +#define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \ + (1 << CTRL2_LOWPWR_SHIFT)) + +/* MAX14577 CONTROL3 register */ +#define CTRL3_JIGSET_SHIFT 0 +#define CTRL3_BOOTSET_SHIFT 2 +#define CTRL3_ADCDBSET_SHIFT 4 +#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT) +#define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT) +#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT) + +/* Slave addr = 0x4A: Charger */ +enum max14577_charger_reg { + MAX14577_CHG_REG_STATUS3 = 0x06, + MAX14577_CHG_REG_CHG_CTRL1 = 0x0F, + MAX14577_CHG_REG_CHG_CTRL2 = 0x10, + MAX14577_CHG_REG_CHG_CTRL3 = 0x11, + MAX14577_CHG_REG_CHG_CTRL4 = 0x12, + MAX14577_CHG_REG_CHG_CTRL5 = 0x13, + MAX14577_CHG_REG_CHG_CTRL6 = 0x14, + MAX14577_CHG_REG_CHG_CTRL7 = 0x15, + + MAX14577_CHG_REG_END, +}; + +/* MAX14577 STATUS3 register */ +#define STATUS3_EOC_SHIFT 0 +#define STATUS3_CGMBC_SHIFT 1 +#define STATUS3_OVP_SHIFT 2 +#define STATUS3_MBCCHGERR_SHIFT 3 +#define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT) +#define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT) +#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT) +#define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT) + +/* MAX14577 CDETCTRL1 register */ +#define CDETCTRL1_CHGDETEN_SHIFT 0 +#define CDETCTRL1_CHGTYPMAN_SHIFT 1 +#define CDETCTRL1_DCDEN_SHIFT 2 +#define CDETCTRL1_DCD2SCT_SHIFT 3 +#define CDETCTRL1_DCHKTM_SHIFT 4 +#define CDETCTRL1_DBEXIT_SHIFT 5 +#define CDETCTRL1_DBIDLE_SHIFT 6 +#define CDETCTRL1_CDPDET_SHIFT 7 +#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT) +#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT) +#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT) +#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT) +#define CDETCTRL1_DCHKTM_MASK (0x1 << CDETCTRL1_DCHKTM_SHIFT) +#define CDETCTRL1_DBEXIT_MASK (0x1 << CDETCTRL1_DBEXIT_SHIFT) +#define CDETCTRL1_DBIDLE_MASK (0x1 << CDETCTRL1_DBIDLE_SHIFT) +#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT) + +/* MAX14577 CHGCTRL1 register */ +#define CHGCTRL1_TCHW_SHIFT 4 +#define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT) + +/* MAX14577 CHGCTRL2 register */ +#define CHGCTRL2_MBCHOSTEN_SHIFT 6 +#define CHGCTRL2_MBCHOSTEN_MASK (0x1 << CHGCTRL2_MBCHOSTEN_SHIFT) +#define CHGCTRL2_VCHGR_RC_SHIFT 7 +#define CHGCTRL2_VCHGR_RC_MASK (0x1 << CHGCTRL2_VCHGR_RC_SHIFT) + +/* MAX14577 CHGCTRL3 register */ +#define CHGCTRL3_MBCCVWRC_SHIFT 0 +#define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT) + +/* MAX14577 CHGCTRL4 register */ +#define CHGCTRL4_MBCICHWRCH_SHIFT 0 +#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT) +#define CHGCTRL4_MBCICHWRCL_SHIFT 4 +#define CHGCTRL4_MBCICHWRCL_MASK (0x1 << CHGCTRL4_MBCICHWRCL_SHIFT) + +/* MAX14577 CHGCTRL5 register */ +#define CHGCTRL5_EOCS_SHIFT 0 +#define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT) + +/* MAX14577 CHGCTRL6 register */ +#define CHGCTRL6_AUTOSTOP_SHIFT 5 +#define CHGCTRL6_AUTOSTOP_MASK (0x1 << CHGCTRL6_AUTOSTOP_SHIFT) + +/* MAX14577 CHGCTRL7 register */ +#define CHGCTRL7_OTPCGHCVS_SHIFT 0 +#define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT) + +/* MAX14577 regulator current limits (as in CHGCTRL4 register), uA */ +#define MAX14577_REGULATOR_CURRENT_LIMIT_MIN 90000 +#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_START 200000 +#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000 +#define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000 + +/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */ +#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000 + +enum max14577_irq { + /* INT1 */ + MAX14577_IRQ_INT1_ADC, + MAX14577_IRQ_INT1_ADCLOW, + MAX14577_IRQ_INT1_ADCERR, + + /* INT2 */ + MAX14577_IRQ_INT2_CHGTYP, + MAX14577_IRQ_INT2_CHGDETRUN, + MAX14577_IRQ_INT2_DCDTMR, + MAX14577_IRQ_INT2_DBCHG, + MAX14577_IRQ_INT2_VBVOLT, + + /* INT3 */ + MAX14577_IRQ_INT3_EOC, + MAX14577_IRQ_INT3_CGMBC, + MAX14577_IRQ_INT3_OVP, + MAX14577_IRQ_INT3_MBCCHGERR, + + MAX14577_IRQ_NUM, +}; + +struct max14577 { + struct device *dev; + struct i2c_client *i2c; /* Slave addr = 0x4A */ + + struct regmap *regmap; + + struct regmap_irq_chip_data *irq_data; + int irq; + + /* Device ID */ + u8 vendor_id; /* Vendor Identification */ + u8 device_id; /* Chip Version */ +}; + +/* MAX14577 shared regmap API function */ +static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest) +{ + unsigned int val; + int ret; + + ret = regmap_read(map, reg, &val); + *dest = val; + + return ret; +} + +static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf, + int count) +{ + return regmap_bulk_read(map, reg, buf, count); +} + +static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value) +{ + return regmap_write(map, reg, value); +} + +static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf, + int count) +{ + return regmap_bulk_write(map, reg, buf, count); +} + +static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask, + u8 val) +{ + return regmap_update_bits(map, reg, mask, val); +} + +#endif /* __MAX14577_PRIVATE_H__ */ diff --git a/include/linux/mfd/max14577.h b/include/linux/mfd/max14577.h new file mode 100644 index 000000000000..736d39c3ec0d --- /dev/null +++ b/include/linux/mfd/max14577.h @@ -0,0 +1,64 @@ +/* + * max14577.h - Driver for the Maxim 14577 + * + * Copyright (C) 2013 Samsung Electrnoics + * Chanwoo Choi <cw00.choi@samsung.com> + * Krzysztof Kozlowski <k.kozlowski@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * This driver is based on max8997.h + * + * MAX14577 has MUIC, Charger devices. + * The devices share the same I2C bus and interrupt line + * included in this mfd driver. + */ + +#ifndef __MAX14577_H__ +#define __MAX14577_H__ + +#include <linux/regulator/consumer.h> + +/* MAX14577 regulator IDs */ +enum max14577_regulators { + MAX14577_SAFEOUT = 0, + MAX14577_CHARGER, + + MAX14577_REG_MAX, +}; + +struct max14577_regulator_platform_data { + int id; + struct regulator_init_data *initdata; + struct device_node *of_node; +}; + +/* + * MAX14577 MFD platform data + */ +struct max14577_platform_data { + /* IRQ */ + int irq_base; + + /* current control GPIOs */ + int gpio_pogo_vbatt_en; + int gpio_pogo_vbus_en; + + /* current control GPIO control function */ + int (*set_gpio_pogo_vbatt_en) (int gpio_val); + int (*set_gpio_pogo_vbus_en) (int gpio_val); + + int (*set_gpio_pogo_cb) (int new_dev); + + struct max14577_regulator_platform_data *regulators; +}; + +#endif /* __MAX14577_H__ */ diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h index d327d4971e4f..8c75a9c8dfab 100644 --- a/include/linux/mfd/max77686-private.h +++ b/include/linux/mfd/max77686-private.h @@ -1,5 +1,5 @@ /* - * max77686.h - Voltage regulator driver for the Maxim 77686 + * max77686-private.h - Voltage regulator driver for the Maxim 77686 * * Copyright (C) 2012 Samsung Electrnoics * Chiwoong Byun <woong.byun@samsung.com> diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h index fb465dfbb59e..78c76cd4d37b 100644 --- a/include/linux/mfd/max8997-private.h +++ b/include/linux/mfd/max8997-private.h @@ -1,5 +1,5 @@ /* - * max8997.h - Voltage regulator driver for the Maxim 8997 + * max8997-private.h - Voltage regulator driver for the Maxim 8997 * * Copyright (C) 2010 Samsung Electrnoics * MyungJoo Ham <myungjoo.ham@samsung.com> @@ -387,7 +387,7 @@ struct max8997_dev { struct i2c_client *muic; /* slave addr 0x4a */ struct mutex iolock; - int type; + unsigned long type; struct platform_device *battery; /* battery control (not fuel gauge) */ int irq; diff --git a/include/linux/mfd/max8998-private.h b/include/linux/mfd/max8998-private.h index 84844e0a5704..d68ada502ff3 100644 --- a/include/linux/mfd/max8998-private.h +++ b/include/linux/mfd/max8998-private.h @@ -1,5 +1,5 @@ /* - * max8998.h - Voltage regulator driver for the Maxim 8998 + * max8998-private.h - Voltage regulator driver for the Maxim 8998 * * Copyright (C) 2009-2010 Samsung Electrnoics * Kyungmin Park <kyungmin.park@samsung.com> @@ -163,7 +163,7 @@ struct max8998_dev { int ono; u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS]; u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS]; - int type; + unsigned long type; bool wakeup; }; diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h index 67c17b5a6f44..a326c850f046 100644 --- a/include/linux/mfd/mc13xxx.h +++ b/include/linux/mfd/mc13xxx.h @@ -21,8 +21,6 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val); int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset, u32 mask, u32 val); -int mc13xxx_get_flags(struct mc13xxx *mc13xxx); - int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq, irq_handler_t handler, const char *name, void *dev); int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq, @@ -106,15 +104,15 @@ enum { MC13892_LED_R, MC13892_LED_G, MC13892_LED_B, + /* MC34708 LED IDs */ + MC34708_LED_R, + MC34708_LED_G, }; struct mc13xxx_led_platform_data { int id; const char *name; const char *default_trigger; - -/* Three or two bits current selection depending on the led */ - char max_current; }; #define MAX_LED_CONTROL_REGS 6 @@ -123,7 +121,7 @@ struct mc13xxx_leds_platform_data { struct mc13xxx_led_platform_data *led; int num_leds; -/* LED Control 0 */ +/* MC13783 LED Control 0 */ #define MC13783_LED_C0_ENABLE (1 << 0) #define MC13783_LED_C0_TRIODE_MD (1 << 7) #define MC13783_LED_C0_TRIODE_AD (1 << 8) @@ -131,21 +129,46 @@ struct mc13xxx_leds_platform_data { #define MC13783_LED_C0_BOOST (1 << 10) #define MC13783_LED_C0_ABMODE(x) (((x) & 0x7) << 11) #define MC13783_LED_C0_ABREF(x) (((x) & 0x3) << 14) -/* LED Control 1 */ +/* MC13783 LED Control 1 */ #define MC13783_LED_C1_TC1HALF (1 << 18) #define MC13783_LED_C1_SLEWLIM (1 << 23) -/* LED Control 2 */ +/* MC13783 LED Control 2 */ +#define MC13783_LED_C2_CURRENT_MD(x) (((x) & 0x7) << 0) +#define MC13783_LED_C2_CURRENT_AD(x) (((x) & 0x7) << 3) +#define MC13783_LED_C2_CURRENT_KP(x) (((x) & 0x7) << 6) #define MC13783_LED_C2_PERIOD(x) (((x) & 0x3) << 21) #define MC13783_LED_C2_SLEWLIM (1 << 23) -/* LED Control 3 */ +/* MC13783 LED Control 3 */ +#define MC13783_LED_C3_CURRENT_R1(x) (((x) & 0x3) << 0) +#define MC13783_LED_C3_CURRENT_G1(x) (((x) & 0x3) << 2) +#define MC13783_LED_C3_CURRENT_B1(x) (((x) & 0x3) << 4) #define MC13783_LED_C3_PERIOD(x) (((x) & 0x3) << 21) #define MC13783_LED_C3_TRIODE_TC1 (1 << 23) -/* LED Control 4 */ +/* MC13783 LED Control 4 */ +#define MC13783_LED_C4_CURRENT_R2(x) (((x) & 0x3) << 0) +#define MC13783_LED_C4_CURRENT_G2(x) (((x) & 0x3) << 2) +#define MC13783_LED_C4_CURRENT_B2(x) (((x) & 0x3) << 4) #define MC13783_LED_C4_PERIOD(x) (((x) & 0x3) << 21) #define MC13783_LED_C4_TRIODE_TC2 (1 << 23) -/* LED Control 5 */ +/* MC13783 LED Control 5 */ +#define MC13783_LED_C5_CURRENT_R3(x) (((x) & 0x3) << 0) +#define MC13783_LED_C5_CURRENT_G3(x) (((x) & 0x3) << 2) +#define MC13783_LED_C5_CURRENT_B3(x) (((x) & 0x3) << 4) #define MC13783_LED_C5_PERIOD(x) (((x) & 0x3) << 21) #define MC13783_LED_C5_TRIODE_TC3 (1 << 23) +/* MC13892 LED Control 0 */ +#define MC13892_LED_C0_CURRENT_MD(x) (((x) & 0x7) << 9) +#define MC13892_LED_C0_CURRENT_AD(x) (((x) & 0x7) << 21) +/* MC13892 LED Control 1 */ +#define MC13892_LED_C1_CURRENT_KP(x) (((x) & 0x7) << 9) +/* MC13892 LED Control 2 */ +#define MC13892_LED_C2_CURRENT_R(x) (((x) & 0x7) << 9) +#define MC13892_LED_C2_CURRENT_G(x) (((x) & 0x7) << 21) +/* MC13892 LED Control 3 */ +#define MC13892_LED_C3_CURRENT_B(x) (((x) & 0x7) << 9) +/* MC34708 LED Control 0 */ +#define MC34708_LED_C0_CURRENT_R(x) (((x) & 0x3) << 9) +#define MC34708_LED_C0_CURRENT_G(x) (((x) & 0x3) << 21) u32 led_control[MAX_LED_CONTROL_REGS]; }; diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h deleted file mode 100644 index f83d6b43ecbb..000000000000 --- a/include/linux/mfd/pm8xxx/irq.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* - * Qualcomm PMIC irq 8xxx driver header file - * - */ - -#ifndef __MFD_PM8XXX_IRQ_H -#define __MFD_PM8XXX_IRQ_H - -#include <linux/errno.h> -#include <linux/err.h> - -struct pm8xxx_irq_core_data { - u32 rev; - int nirqs; -}; - -struct pm8xxx_irq_platform_data { - int irq_base; - struct pm8xxx_irq_core_data irq_cdata; - int devirq; - int irq_trigger_flag; -}; - -struct pm_irq_chip; - -#ifdef CONFIG_MFD_PM8XXX_IRQ -int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq); -struct pm_irq_chip *pm8xxx_irq_init(struct device *dev, - const struct pm8xxx_irq_platform_data *pdata); -int pm8xxx_irq_exit(struct pm_irq_chip *chip); -#else -static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq) -{ - return -ENXIO; -} -static inline struct pm_irq_chip *pm8xxx_irq_init( - const struct device *dev, - const struct pm8xxx_irq_platform_data *pdata) -{ - return ERR_PTR(-ENXIO); -} -static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip) -{ - return -ENXIO; -} -#endif /* CONFIG_MFD_PM8XXX_IRQ */ -#endif /* __MFD_PM8XXX_IRQ_H */ diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h deleted file mode 100644 index 00fa3de7659d..000000000000 --- a/include/linux/mfd/pm8xxx/pm8921.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/* - * Qualcomm PMIC 8921 driver header file - * - */ - -#ifndef __MFD_PM8921_H -#define __MFD_PM8921_H - -#include <linux/mfd/pm8xxx/irq.h> - -#define PM8921_NR_IRQS 256 - -struct pm8921_platform_data { - int irq_base; - struct pm8xxx_irq_platform_data *irq_pdata; -}; - -#endif diff --git a/include/linux/mfd/pm8xxx/rtc.h b/include/linux/mfd/pm8xxx/rtc.h deleted file mode 100644 index 14f1983eaecc..000000000000 --- a/include/linux/mfd/pm8xxx/rtc.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __RTC_PM8XXX_H__ -#define __RTC_PM8XXX_H__ - -#define PM8XXX_RTC_DEV_NAME "rtc-pm8xxx" -/** - * struct pm8xxx_rtc_pdata - RTC driver platform data - * @rtc_write_enable: variable stating RTC write capability - */ -struct pm8xxx_rtc_platform_data { - bool rtc_write_enable; -}; - -#endif /* __RTC_PM8XXX_H__ */ diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h index 443176ee1ab0..7c36cc55d2c7 100644 --- a/include/linux/mfd/rtsx_common.h +++ b/include/linux/mfd/rtsx_common.h @@ -45,6 +45,7 @@ struct platform_device; struct rtsx_slot { struct platform_device *p_dev; void (*card_event)(struct platform_device *p_dev); + void (*done_transfer)(struct platform_device *p_dev); }; #endif diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h index 0ce772105508..8d6bbd609ad9 100644 --- a/include/linux/mfd/rtsx_pci.h +++ b/include/linux/mfd/rtsx_pci.h @@ -144,7 +144,7 @@ #define HOST_TO_DEVICE 0 #define DEVICE_TO_HOST 1 -#define MAX_PHASE 31 +#define RTSX_PHASE_MAX 32 #define RX_TUNING_CNT 3 /* SG descriptor */ @@ -943,6 +943,12 @@ void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr); int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout); int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, int num_sg, bool read, int timeout); +int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, + int num_sg, bool read); +int rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, + int num_sg, bool read); +int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, + int sg_count, bool read); int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card); diff --git a/include/linux/mfd/rtsx_usb.h b/include/linux/mfd/rtsx_usb.h new file mode 100644 index 000000000000..c446e4fd6b5c --- /dev/null +++ b/include/linux/mfd/rtsx_usb.h @@ -0,0 +1,628 @@ +/* Driver for Realtek RTS5139 USB card reader + * + * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + * + * Author: + * Roger Tseng <rogerable@realtek.com> + */ + +#ifndef __RTSX_USB_H +#define __RTSX_USB_H + +#include <linux/usb.h> + +/* related module names */ +#define RTSX_USB_SD_CARD 0 +#define RTSX_USB_MS_CARD 1 + +/* endpoint numbers */ +#define EP_BULK_OUT 1 +#define EP_BULK_IN 2 +#define EP_INTR_IN 3 + +/* USB vendor requests */ +#define RTSX_USB_REQ_REG_OP 0x00 +#define RTSX_USB_REQ_POLL 0x02 + +/* miscellaneous parameters */ +#define MIN_DIV_N 60 +#define MAX_DIV_N 120 + +#define MAX_PHASE 15 +#define RX_TUNING_CNT 3 + +#define QFN24 0 +#define LQFP48 1 +#define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg)) + +/* data structures */ +struct rtsx_ucr { + u16 vendor_id; + u16 product_id; + + int package; + u8 ic_version; + bool is_rts5179; + + unsigned int cur_clk; + + u8 *cmd_buf; + unsigned int cmd_idx; + u8 *rsp_buf; + + struct usb_device *pusb_dev; + struct usb_interface *pusb_intf; + struct usb_sg_request current_sg; + unsigned char *iobuf; + dma_addr_t iobuf_dma; + + struct timer_list sg_timer; + struct mutex dev_mutex; +}; + +/* buffer size */ +#define IOBUF_SIZE 1024 + +/* prototypes of exported functions */ +extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status); + +extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data); +extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask, + u8 data); + +extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask, + u8 data); +extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr, + u8 *data); + +extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type, + u16 reg_addr, u8 mask, u8 data); +extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout); +extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout); +extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe, + void *buf, unsigned int len, int use_sg, + unsigned int *act_len, int timeout); + +extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len); +extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len); +extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock, + u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); +extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card); + +/* card status */ +#define SD_CD 0x01 +#define MS_CD 0x02 +#define XD_CD 0x04 +#define CD_MASK (SD_CD | MS_CD | XD_CD) +#define SD_WP 0x08 + +/* reader command field offset & parameters */ +#define READ_REG_CMD 0 +#define WRITE_REG_CMD 1 +#define CHECK_REG_CMD 2 + +#define PACKET_TYPE 4 +#define CNT_H 5 +#define CNT_L 6 +#define STAGE_FLAG 7 +#define CMD_OFFSET 8 +#define SEQ_WRITE_DATA_OFFSET 12 + +#define BATCH_CMD 0 +#define SEQ_READ 1 +#define SEQ_WRITE 2 + +#define STAGE_R 0x01 +#define STAGE_DI 0x02 +#define STAGE_DO 0x04 +#define STAGE_MS_STATUS 0x08 +#define STAGE_XD_STATUS 0x10 +#define MODE_C 0x00 +#define MODE_CR (STAGE_R) +#define MODE_CDIR (STAGE_R | STAGE_DI) +#define MODE_CDOR (STAGE_R | STAGE_DO) + +#define EP0_OP_SHIFT 14 +#define EP0_READ_REG_CMD 2 +#define EP0_WRITE_REG_CMD 3 + +#define rtsx_usb_cmd_hdr_tag(ucr) \ + do { \ + ucr->cmd_buf[0] = 'R'; \ + ucr->cmd_buf[1] = 'T'; \ + ucr->cmd_buf[2] = 'C'; \ + ucr->cmd_buf[3] = 'R'; \ + } while (0) + +static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr) +{ + rtsx_usb_cmd_hdr_tag(ucr); + ucr->cmd_idx = 0; + ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD; +} + +/* internal register address */ +#define FPDCTL 0xFC00 +#define SSC_DIV_N_0 0xFC07 +#define SSC_CTL1 0xFC09 +#define SSC_CTL2 0xFC0A +#define CFG_MODE 0xFC0E +#define CFG_MODE_1 0xFC0F +#define RCCTL 0xFC14 +#define SOF_WDOG 0xFC28 +#define SYS_DUMMY0 0xFC30 + +#define MS_BLKEND 0xFD30 +#define MS_READ_START 0xFD31 +#define MS_READ_COUNT 0xFD32 +#define MS_WRITE_START 0xFD33 +#define MS_WRITE_COUNT 0xFD34 +#define MS_COMMAND 0xFD35 +#define MS_OLD_BLOCK_0 0xFD36 +#define MS_OLD_BLOCK_1 0xFD37 +#define MS_NEW_BLOCK_0 0xFD38 +#define MS_NEW_BLOCK_1 0xFD39 +#define MS_LOG_BLOCK_0 0xFD3A +#define MS_LOG_BLOCK_1 0xFD3B +#define MS_BUS_WIDTH 0xFD3C +#define MS_PAGE_START 0xFD3D +#define MS_PAGE_LENGTH 0xFD3E +#define MS_CFG 0xFD40 +#define MS_TPC 0xFD41 +#define MS_TRANS_CFG 0xFD42 +#define MS_TRANSFER 0xFD43 +#define MS_INT_REG 0xFD44 +#define MS_BYTE_CNT 0xFD45 +#define MS_SECTOR_CNT_L 0xFD46 +#define MS_SECTOR_CNT_H 0xFD47 +#define MS_DBUS_H 0xFD48 + +#define CARD_DMA1_CTL 0xFD5C +#define CARD_PULL_CTL1 0xFD60 +#define CARD_PULL_CTL2 0xFD61 +#define CARD_PULL_CTL3 0xFD62 +#define CARD_PULL_CTL4 0xFD63 +#define CARD_PULL_CTL5 0xFD64 +#define CARD_PULL_CTL6 0xFD65 +#define CARD_EXIST 0xFD6F +#define CARD_INT_PEND 0xFD71 + +#define LDO_POWER_CFG 0xFD7B + +#define SD_CFG1 0xFDA0 +#define SD_CFG2 0xFDA1 +#define SD_CFG3 0xFDA2 +#define SD_STAT1 0xFDA3 +#define SD_STAT2 0xFDA4 +#define SD_BUS_STAT 0xFDA5 +#define SD_PAD_CTL 0xFDA6 +#define SD_SAMPLE_POINT_CTL 0xFDA7 +#define SD_PUSH_POINT_CTL 0xFDA8 +#define SD_CMD0 0xFDA9 +#define SD_CMD1 0xFDAA +#define SD_CMD2 0xFDAB +#define SD_CMD3 0xFDAC +#define SD_CMD4 0xFDAD +#define SD_CMD5 0xFDAE +#define SD_BYTE_CNT_L 0xFDAF +#define SD_BYTE_CNT_H 0xFDB0 +#define SD_BLOCK_CNT_L 0xFDB1 +#define SD_BLOCK_CNT_H 0xFDB2 +#define SD_TRANSFER 0xFDB3 +#define SD_CMD_STATE 0xFDB5 +#define SD_DATA_STATE 0xFDB6 +#define SD_VPCLK0_CTL 0xFC2A +#define SD_VPCLK1_CTL 0xFC2B +#define SD_DCMPS0_CTL 0xFC2C +#define SD_DCMPS1_CTL 0xFC2D + +#define CARD_DMA1_CTL 0xFD5C + +#define HW_VERSION 0xFC01 + +#define SSC_CLK_FPGA_SEL 0xFC02 +#define CLK_DIV 0xFC03 +#define SFSM_ED 0xFC04 + +#define CD_DEGLITCH_WIDTH 0xFC20 +#define CD_DEGLITCH_EN 0xFC21 +#define AUTO_DELINK_EN 0xFC23 + +#define FPGA_PULL_CTL 0xFC1D +#define CARD_CLK_SOURCE 0xFC2E + +#define CARD_SHARE_MODE 0xFD51 +#define CARD_DRIVE_SEL 0xFD52 +#define CARD_STOP 0xFD53 +#define CARD_OE 0xFD54 +#define CARD_AUTO_BLINK 0xFD55 +#define CARD_GPIO 0xFD56 +#define SD30_DRIVE_SEL 0xFD57 + +#define CARD_DATA_SOURCE 0xFD5D +#define CARD_SELECT 0xFD5E + +#define CARD_CLK_EN 0xFD79 +#define CARD_PWR_CTL 0xFD7A + +#define OCPCTL 0xFD80 +#define OCPPARA1 0xFD81 +#define OCPPARA2 0xFD82 +#define OCPSTAT 0xFD83 + +#define HS_USB_STAT 0xFE01 +#define HS_VCONTROL 0xFE26 +#define HS_VSTAIN 0xFE27 +#define HS_VLOADM 0xFE28 +#define HS_VSTAOUT 0xFE29 + +#define MC_IRQ 0xFF00 +#define MC_IRQEN 0xFF01 +#define MC_FIFO_CTL 0xFF02 +#define MC_FIFO_BC0 0xFF03 +#define MC_FIFO_BC1 0xFF04 +#define MC_FIFO_STAT 0xFF05 +#define MC_FIFO_MODE 0xFF06 +#define MC_FIFO_RD_PTR0 0xFF07 +#define MC_FIFO_RD_PTR1 0xFF08 +#define MC_DMA_CTL 0xFF10 +#define MC_DMA_TC0 0xFF11 +#define MC_DMA_TC1 0xFF12 +#define MC_DMA_TC2 0xFF13 +#define MC_DMA_TC3 0xFF14 +#define MC_DMA_RST 0xFF15 + +#define RBUF_SIZE_MASK 0xFBFF +#define RBUF_BASE 0xF000 +#define PPBUF_BASE1 0xF800 +#define PPBUF_BASE2 0xFA00 + +/* internal register value macros */ +#define POWER_OFF 0x03 +#define PARTIAL_POWER_ON 0x02 +#define POWER_ON 0x00 +#define POWER_MASK 0x03 +#define LDO3318_PWR_MASK 0x0C +#define LDO_ON 0x00 +#define LDO_SUSPEND 0x08 +#define LDO_OFF 0x0C +#define DV3318_AUTO_PWR_OFF 0x10 +#define FORCE_LDO_POWERB 0x60 + +/* LDO_POWER_CFG */ +#define TUNE_SD18_MASK 0x1C +#define TUNE_SD18_1V7 0x00 +#define TUNE_SD18_1V8 (0x01 << 2) +#define TUNE_SD18_1V9 (0x02 << 2) +#define TUNE_SD18_2V0 (0x03 << 2) +#define TUNE_SD18_2V7 (0x04 << 2) +#define TUNE_SD18_2V8 (0x05 << 2) +#define TUNE_SD18_2V9 (0x06 << 2) +#define TUNE_SD18_3V3 (0x07 << 2) + +/* CLK_DIV */ +#define CLK_CHANGE 0x80 +#define CLK_DIV_1 0x00 +#define CLK_DIV_2 0x01 +#define CLK_DIV_4 0x02 +#define CLK_DIV_8 0x03 + +#define SSC_POWER_MASK 0x01 +#define SSC_POWER_DOWN 0x01 +#define SSC_POWER_ON 0x00 + +#define FPGA_VER 0x80 +#define HW_VER_MASK 0x0F + +#define EXTEND_DMA1_ASYNC_SIGNAL 0x02 + +/* CFG_MODE*/ +#define XTAL_FREE 0x80 +#define CLK_MODE_MASK 0x03 +#define CLK_MODE_12M_XTAL 0x00 +#define CLK_MODE_NON_XTAL 0x01 +#define CLK_MODE_24M_OSC 0x02 +#define CLK_MODE_48M_OSC 0x03 + +/* CFG_MODE_1*/ +#define RTS5179 0x02 + +#define NYET_EN 0x01 +#define NYET_MSAK 0x01 + +#define SD30_DRIVE_MASK 0x07 +#define SD20_DRIVE_MASK 0x03 + +#define DISABLE_SD_CD 0x08 +#define DISABLE_MS_CD 0x10 +#define DISABLE_XD_CD 0x20 +#define SD_CD_DEGLITCH_EN 0x01 +#define MS_CD_DEGLITCH_EN 0x02 +#define XD_CD_DEGLITCH_EN 0x04 + +#define CARD_SHARE_LQFP48 0x04 +#define CARD_SHARE_QFN24 0x00 +#define CARD_SHARE_LQFP_SEL 0x04 +#define CARD_SHARE_XD 0x00 +#define CARD_SHARE_SD 0x01 +#define CARD_SHARE_MS 0x02 +#define CARD_SHARE_MASK 0x03 + + +/* SD30_DRIVE_SEL */ +#define DRIVER_TYPE_A 0x05 +#define DRIVER_TYPE_B 0x03 +#define DRIVER_TYPE_C 0x02 +#define DRIVER_TYPE_D 0x01 + +/* SD_BUS_STAT */ +#define SD_CLK_TOGGLE_EN 0x80 +#define SD_CLK_FORCE_STOP 0x40 +#define SD_DAT3_STATUS 0x10 +#define SD_DAT2_STATUS 0x08 +#define SD_DAT1_STATUS 0x04 +#define SD_DAT0_STATUS 0x02 +#define SD_CMD_STATUS 0x01 + +/* SD_PAD_CTL */ +#define SD_IO_USING_1V8 0x80 +#define SD_IO_USING_3V3 0x7F +#define TYPE_A_DRIVING 0x00 +#define TYPE_B_DRIVING 0x01 +#define TYPE_C_DRIVING 0x02 +#define TYPE_D_DRIVING 0x03 + +/* CARD_CLK_EN */ +#define SD_CLK_EN 0x04 +#define MS_CLK_EN 0x08 + +/* CARD_SELECT */ +#define SD_MOD_SEL 2 +#define MS_MOD_SEL 3 + +/* CARD_SHARE_MODE */ +#define CARD_SHARE_LQFP48 0x04 +#define CARD_SHARE_QFN24 0x00 +#define CARD_SHARE_LQFP_SEL 0x04 +#define CARD_SHARE_XD 0x00 +#define CARD_SHARE_SD 0x01 +#define CARD_SHARE_MS 0x02 +#define CARD_SHARE_MASK 0x03 + +/* SSC_CTL1 */ +#define SSC_RSTB 0x80 +#define SSC_8X_EN 0x40 +#define SSC_FIX_FRAC 0x20 +#define SSC_SEL_1M 0x00 +#define SSC_SEL_2M 0x08 +#define SSC_SEL_4M 0x10 +#define SSC_SEL_8M 0x18 + +/* SSC_CTL2 */ +#define SSC_DEPTH_MASK 0x03 +#define SSC_DEPTH_DISALBE 0x00 +#define SSC_DEPTH_2M 0x01 +#define SSC_DEPTH_1M 0x02 +#define SSC_DEPTH_512K 0x03 + +/* SD_VPCLK0_CTL */ +#define PHASE_CHANGE 0x80 +#define PHASE_NOT_RESET 0x40 + +/* SD_TRANSFER */ +#define SD_TRANSFER_START 0x80 +#define SD_TRANSFER_END 0x40 +#define SD_STAT_IDLE 0x20 +#define SD_TRANSFER_ERR 0x10 +#define SD_TM_NORMAL_WRITE 0x00 +#define SD_TM_AUTO_WRITE_3 0x01 +#define SD_TM_AUTO_WRITE_4 0x02 +#define SD_TM_AUTO_READ_3 0x05 +#define SD_TM_AUTO_READ_4 0x06 +#define SD_TM_CMD_RSP 0x08 +#define SD_TM_AUTO_WRITE_1 0x09 +#define SD_TM_AUTO_WRITE_2 0x0A +#define SD_TM_NORMAL_READ 0x0C +#define SD_TM_AUTO_READ_1 0x0D +#define SD_TM_AUTO_READ_2 0x0E +#define SD_TM_AUTO_TUNING 0x0F + +/* SD_CFG1 */ +#define SD_CLK_DIVIDE_0 0x00 +#define SD_CLK_DIVIDE_256 0xC0 +#define SD_CLK_DIVIDE_128 0x80 +#define SD_CLK_DIVIDE_MASK 0xC0 +#define SD_BUS_WIDTH_1BIT 0x00 +#define SD_BUS_WIDTH_4BIT 0x01 +#define SD_BUS_WIDTH_8BIT 0x02 +#define SD_ASYNC_FIFO_RST 0x10 +#define SD_20_MODE 0x00 +#define SD_DDR_MODE 0x04 +#define SD_30_MODE 0x08 + +/* SD_CFG2 */ +#define SD_CALCULATE_CRC7 0x00 +#define SD_NO_CALCULATE_CRC7 0x80 +#define SD_CHECK_CRC16 0x00 +#define SD_NO_CHECK_CRC16 0x40 +#define SD_WAIT_CRC_TO_EN 0x20 +#define SD_WAIT_BUSY_END 0x08 +#define SD_NO_WAIT_BUSY_END 0x00 +#define SD_CHECK_CRC7 0x00 +#define SD_NO_CHECK_CRC7 0x04 +#define SD_RSP_LEN_0 0x00 +#define SD_RSP_LEN_6 0x01 +#define SD_RSP_LEN_17 0x02 +#define SD_RSP_TYPE_R0 0x04 +#define SD_RSP_TYPE_R1 0x01 +#define SD_RSP_TYPE_R1b 0x09 +#define SD_RSP_TYPE_R2 0x02 +#define SD_RSP_TYPE_R3 0x05 +#define SD_RSP_TYPE_R4 0x05 +#define SD_RSP_TYPE_R5 0x01 +#define SD_RSP_TYPE_R6 0x01 +#define SD_RSP_TYPE_R7 0x01 + +/* SD_STAT1 */ +#define SD_CRC7_ERR 0x80 +#define SD_CRC16_ERR 0x40 +#define SD_CRC_WRITE_ERR 0x20 +#define SD_CRC_WRITE_ERR_MASK 0x1C +#define GET_CRC_TIME_OUT 0x02 +#define SD_TUNING_COMPARE_ERR 0x01 + +/* SD_DATA_STATE */ +#define SD_DATA_IDLE 0x80 + +/* CARD_DATA_SOURCE */ +#define PINGPONG_BUFFER 0x01 +#define RING_BUFFER 0x00 + +/* CARD_OE */ +#define SD_OUTPUT_EN 0x04 +#define MS_OUTPUT_EN 0x08 + +/* CARD_STOP */ +#define SD_STOP 0x04 +#define MS_STOP 0x08 +#define SD_CLR_ERR 0x40 +#define MS_CLR_ERR 0x80 + +/* CARD_CLK_SOURCE */ +#define CRC_FIX_CLK (0x00 << 0) +#define CRC_VAR_CLK0 (0x01 << 0) +#define CRC_VAR_CLK1 (0x02 << 0) +#define SD30_FIX_CLK (0x00 << 2) +#define SD30_VAR_CLK0 (0x01 << 2) +#define SD30_VAR_CLK1 (0x02 << 2) +#define SAMPLE_FIX_CLK (0x00 << 4) +#define SAMPLE_VAR_CLK0 (0x01 << 4) +#define SAMPLE_VAR_CLK1 (0x02 << 4) + +/* SD_SAMPLE_POINT_CTL */ +#define DDR_FIX_RX_DAT 0x00 +#define DDR_VAR_RX_DAT 0x80 +#define DDR_FIX_RX_DAT_EDGE 0x00 +#define DDR_FIX_RX_DAT_14_DELAY 0x40 +#define DDR_FIX_RX_CMD 0x00 +#define DDR_VAR_RX_CMD 0x20 +#define DDR_FIX_RX_CMD_POS_EDGE 0x00 +#define DDR_FIX_RX_CMD_14_DELAY 0x10 +#define SD20_RX_POS_EDGE 0x00 +#define SD20_RX_14_DELAY 0x08 +#define SD20_RX_SEL_MASK 0x08 + +/* SD_PUSH_POINT_CTL */ +#define DDR_FIX_TX_CMD_DAT 0x00 +#define DDR_VAR_TX_CMD_DAT 0x80 +#define DDR_FIX_TX_DAT_14_TSU 0x00 +#define DDR_FIX_TX_DAT_12_TSU 0x40 +#define DDR_FIX_TX_CMD_NEG_EDGE 0x00 +#define DDR_FIX_TX_CMD_14_AHEAD 0x20 +#define SD20_TX_NEG_EDGE 0x00 +#define SD20_TX_14_AHEAD 0x10 +#define SD20_TX_SEL_MASK 0x10 +#define DDR_VAR_SDCLK_POL_SWAP 0x01 + +/* MS_CFG */ +#define SAMPLE_TIME_RISING 0x00 +#define SAMPLE_TIME_FALLING 0x80 +#define PUSH_TIME_DEFAULT 0x00 +#define PUSH_TIME_ODD 0x40 +#define NO_EXTEND_TOGGLE 0x00 +#define EXTEND_TOGGLE_CHK 0x20 +#define MS_BUS_WIDTH_1 0x00 +#define MS_BUS_WIDTH_4 0x10 +#define MS_BUS_WIDTH_8 0x18 +#define MS_2K_SECTOR_MODE 0x04 +#define MS_512_SECTOR_MODE 0x00 +#define MS_TOGGLE_TIMEOUT_EN 0x00 +#define MS_TOGGLE_TIMEOUT_DISEN 0x01 +#define MS_NO_CHECK_INT 0x02 + +/* MS_TRANS_CFG */ +#define WAIT_INT 0x80 +#define NO_WAIT_INT 0x00 +#define NO_AUTO_READ_INT_REG 0x00 +#define AUTO_READ_INT_REG 0x40 +#define MS_CRC16_ERR 0x20 +#define MS_RDY_TIMEOUT 0x10 +#define MS_INT_CMDNK 0x08 +#define MS_INT_BREQ 0x04 +#define MS_INT_ERR 0x02 +#define MS_INT_CED 0x01 + +/* MS_TRANSFER */ +#define MS_TRANSFER_START 0x80 +#define MS_TRANSFER_END 0x40 +#define MS_TRANSFER_ERR 0x20 +#define MS_BS_STATE 0x10 +#define MS_TM_READ_BYTES 0x00 +#define MS_TM_NORMAL_READ 0x01 +#define MS_TM_WRITE_BYTES 0x04 +#define MS_TM_NORMAL_WRITE 0x05 +#define MS_TM_AUTO_READ 0x08 +#define MS_TM_AUTO_WRITE 0x0C +#define MS_TM_SET_CMD 0x06 +#define MS_TM_COPY_PAGE 0x07 +#define MS_TM_MULTI_READ 0x02 +#define MS_TM_MULTI_WRITE 0x03 + +/* MC_FIFO_CTL */ +#define FIFO_FLUSH 0x01 + +/* MC_DMA_RST */ +#define DMA_RESET 0x01 + +/* MC_DMA_CTL */ +#define DMA_TC_EQ_0 0x80 +#define DMA_DIR_TO_CARD 0x00 +#define DMA_DIR_FROM_CARD 0x02 +#define DMA_EN 0x01 +#define DMA_128 (0 << 2) +#define DMA_256 (1 << 2) +#define DMA_512 (2 << 2) +#define DMA_1024 (3 << 2) +#define DMA_PACK_SIZE_MASK 0x0C + +/* CARD_INT_PEND */ +#define XD_INT 0x10 +#define MS_INT 0x08 +#define SD_INT 0x04 + +/* LED operations*/ +static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr) +{ + return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02); +} + +static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr) +{ + return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03); +} + +/* HW error clearing */ +static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr) +{ + rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8); +} + +static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr) +{ + rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL, + FIFO_FLUSH, FIFO_FLUSH); + rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET); +} +#endif /* __RTS51139_H */ diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h index cab2dd279076..157e32b6ca28 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -18,7 +18,9 @@ enum sec_device_type { S5M8751X, S5M8763X, S5M8767X, + S2MPA01, S2MPS11X, + S2MPS14X, }; /** @@ -50,7 +52,7 @@ struct sec_pmic_dev { struct regmap_irq_chip_data *irq_data; int ono; - int type; + unsigned long type; bool wakeup; bool wtsr_smpl; }; @@ -59,12 +61,6 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic); void sec_irq_exit(struct sec_pmic_dev *sec_pmic); int sec_irq_resume(struct sec_pmic_dev *sec_pmic); -extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u8 reg, void *dest); -extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf); -extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value); -extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u8 reg, int count, u8 *buf); -extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u8 reg, u8 val, u8 mask); - struct sec_platform_data { struct sec_regulator_data *regulators; struct sec_opmode_data *opmode; @@ -98,7 +94,7 @@ struct sec_platform_data { int buck3_default_idx; int buck4_default_idx; - int buck_ramp_delay; + int buck_ramp_delay; int buck2_ramp_delay; int buck34_ramp_delay; @@ -106,10 +102,15 @@ struct sec_platform_data { int buck16_ramp_delay; int buck7810_ramp_delay; int buck9_ramp_delay; - - bool buck2_ramp_enable; - bool buck3_ramp_enable; - bool buck4_ramp_enable; + int buck24_ramp_delay; + int buck3_ramp_delay; + int buck7_ramp_delay; + int buck8910_ramp_delay; + + bool buck1_ramp_enable; + bool buck2_ramp_enable; + bool buck3_ramp_enable; + bool buck4_ramp_enable; bool buck6_ramp_enable; int buck2_init; @@ -125,7 +126,8 @@ struct sec_platform_data { struct sec_regulator_data { int id; struct regulator_init_data *initdata; - struct device_node *reg_node; + struct device_node *reg_node; + int ext_control_gpio; }; /* diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h index d43b4f9e7fb2..1224f447356b 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -13,6 +13,56 @@ #ifndef __LINUX_MFD_SEC_IRQ_H #define __LINUX_MFD_SEC_IRQ_H +enum s2mpa01_irq { + S2MPA01_IRQ_PWRONF, + S2MPA01_IRQ_PWRONR, + S2MPA01_IRQ_JIGONBF, + S2MPA01_IRQ_JIGONBR, + S2MPA01_IRQ_ACOKBF, + S2MPA01_IRQ_ACOKBR, + S2MPA01_IRQ_PWRON1S, + S2MPA01_IRQ_MRB, + + S2MPA01_IRQ_RTC60S, + S2MPA01_IRQ_RTCA1, + S2MPA01_IRQ_RTCA0, + S2MPA01_IRQ_SMPL, + S2MPA01_IRQ_RTC1S, + S2MPA01_IRQ_WTSR, + + S2MPA01_IRQ_INT120C, + S2MPA01_IRQ_INT140C, + S2MPA01_IRQ_LDO3_TSD, + S2MPA01_IRQ_B16_TSD, + S2MPA01_IRQ_B24_TSD, + S2MPA01_IRQ_B35_TSD, + + S2MPA01_IRQ_NR, +}; + +#define S2MPA01_IRQ_PWRONF_MASK (1 << 0) +#define S2MPA01_IRQ_PWRONR_MASK (1 << 1) +#define S2MPA01_IRQ_JIGONBF_MASK (1 << 2) +#define S2MPA01_IRQ_JIGONBR_MASK (1 << 3) +#define S2MPA01_IRQ_ACOKBF_MASK (1 << 4) +#define S2MPA01_IRQ_ACOKBR_MASK (1 << 5) +#define S2MPA01_IRQ_PWRON1S_MASK (1 << 6) +#define S2MPA01_IRQ_MRB_MASK (1 << 7) + +#define S2MPA01_IRQ_RTC60S_MASK (1 << 0) +#define S2MPA01_IRQ_RTCA1_MASK (1 << 1) +#define S2MPA01_IRQ_RTCA0_MASK (1 << 2) +#define S2MPA01_IRQ_SMPL_MASK (1 << 3) +#define S2MPA01_IRQ_RTC1S_MASK (1 << 4) +#define S2MPA01_IRQ_WTSR_MASK (1 << 5) + +#define S2MPA01_IRQ_INT120C_MASK (1 << 0) +#define S2MPA01_IRQ_INT140C_MASK (1 << 1) +#define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2) +#define S2MPA01_IRQ_B16_TSD_MASK (1 << 3) +#define S2MPA01_IRQ_B24_TSD_MASK (1 << 4) +#define S2MPA01_IRQ_B35_TSD_MASK (1 << 5) + enum s2mps11_irq { S2MPS11_IRQ_PWRONF, S2MPS11_IRQ_PWRONR, @@ -24,8 +74,8 @@ enum s2mps11_irq { S2MPS11_IRQ_MRB, S2MPS11_IRQ_RTC60S, + S2MPS11_IRQ_RTCA0, S2MPS11_IRQ_RTCA1, - S2MPS11_IRQ_RTCA2, S2MPS11_IRQ_SMPL, S2MPS11_IRQ_RTC1S, S2MPS11_IRQ_WTSR, @@ -47,7 +97,7 @@ enum s2mps11_irq { #define S2MPS11_IRQ_RTC60S_MASK (1 << 0) #define S2MPS11_IRQ_RTCA1_MASK (1 << 1) -#define S2MPS11_IRQ_RTCA2_MASK (1 << 2) +#define S2MPS11_IRQ_RTCA0_MASK (1 << 2) #define S2MPS11_IRQ_SMPL_MASK (1 << 3) #define S2MPS11_IRQ_RTC1S_MASK (1 << 4) #define S2MPS11_IRQ_WTSR_MASK (1 << 5) @@ -55,6 +105,33 @@ enum s2mps11_irq { #define S2MPS11_IRQ_INT120C_MASK (1 << 0) #define S2MPS11_IRQ_INT140C_MASK (1 << 1) +enum s2mps14_irq { + S2MPS14_IRQ_PWRONF, + S2MPS14_IRQ_PWRONR, + S2MPS14_IRQ_JIGONBF, + S2MPS14_IRQ_JIGONBR, + S2MPS14_IRQ_ACOKBF, + S2MPS14_IRQ_ACOKBR, + S2MPS14_IRQ_PWRON1S, + S2MPS14_IRQ_MRB, + + S2MPS14_IRQ_RTC60S, + S2MPS14_IRQ_RTCA1, + S2MPS14_IRQ_RTCA0, + S2MPS14_IRQ_SMPL, + S2MPS14_IRQ_RTC1S, + S2MPS14_IRQ_WTSR, + + S2MPS14_IRQ_INT120C, + S2MPS14_IRQ_INT140C, + S2MPS14_IRQ_TSD, + + S2MPS14_IRQ_NR, +}; + +/* Masks for interrupts are the same as in s2mps11 */ +#define S2MPS14_IRQ_TSD_MASK (1 << 2) + enum s5m8767_irq { S5M8767_IRQ_PWRR, S5M8767_IRQ_PWRF, diff --git a/include/linux/mfd/samsung/rtc.h b/include/linux/mfd/samsung/rtc.h index 94b7cd6d8891..3e02b768d537 100644 --- a/include/linux/mfd/samsung/rtc.h +++ b/include/linux/mfd/samsung/rtc.h @@ -1,12 +1,17 @@ -/* rtc.h +/* rtc.h * - * Copyright (c) 2011 Samsung Electronics Co., Ltd + * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd * http://www.samsung.com * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * */ @@ -43,6 +48,39 @@ enum sec_rtc_reg { SEC_RTC_STATUS, SEC_WTSR_SMPL_CNTL, SEC_RTC_UDR_CON, + + SEC_RTC_REG_MAX, +}; + +enum s2mps_rtc_reg { + S2MPS_RTC_CTRL, + S2MPS_WTSR_SMPL_CNTL, + S2MPS_RTC_UDR_CON, + S2MPS_RSVD, + S2MPS_RTC_SEC, + S2MPS_RTC_MIN, + S2MPS_RTC_HOUR, + S2MPS_RTC_WEEKDAY, + S2MPS_RTC_DATE, + S2MPS_RTC_MONTH, + S2MPS_RTC_YEAR, + S2MPS_ALARM0_SEC, + S2MPS_ALARM0_MIN, + S2MPS_ALARM0_HOUR, + S2MPS_ALARM0_WEEKDAY, + S2MPS_ALARM0_DATE, + S2MPS_ALARM0_MONTH, + S2MPS_ALARM0_YEAR, + S2MPS_ALARM1_SEC, + S2MPS_ALARM1_MIN, + S2MPS_ALARM1_HOUR, + S2MPS_ALARM1_WEEKDAY, + S2MPS_ALARM1_DATE, + S2MPS_ALARM1_MONTH, + S2MPS_ALARM1_YEAR, + S2MPS_OFFSRC, + + S2MPS_RTC_REG_MAX, }; #define RTC_I2C_ADDR (0x0C >> 1) @@ -54,6 +92,9 @@ enum sec_rtc_reg { #define ALARM1_STATUS (1 << 2) #define UPDATE_AD (1 << 0) +#define S2MPS_ALARM0_STATUS (1 << 2) +#define S2MPS_ALARM1_STATUS (1 << 1) + /* RTC Control Register */ #define BCD_EN_SHIFT 0 #define BCD_EN_MASK (1 << BCD_EN_SHIFT) @@ -62,6 +103,10 @@ enum sec_rtc_reg { /* RTC Update Register1 */ #define RTC_UDR_SHIFT 0 #define RTC_UDR_MASK (1 << RTC_UDR_SHIFT) +#define S2MPS_RTC_WUDR_SHIFT 4 +#define S2MPS_RTC_WUDR_MASK (1 << S2MPS_RTC_WUDR_SHIFT) +#define S2MPS_RTC_RUDR_SHIFT 0 +#define S2MPS_RTC_RUDR_MASK (1 << S2MPS_RTC_RUDR_SHIFT) #define RTC_TCON_SHIFT 1 #define RTC_TCON_MASK (1 << RTC_TCON_SHIFT) #define RTC_TIME_EN_SHIFT 3 diff --git a/include/linux/mfd/samsung/s2mpa01.h b/include/linux/mfd/samsung/s2mpa01.h new file mode 100644 index 000000000000..fbc63bc0d6a2 --- /dev/null +++ b/include/linux/mfd/samsung/s2mpa01.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_S2MPA01_H +#define __LINUX_MFD_S2MPA01_H + +/* S2MPA01 registers */ +enum s2mpa01_reg { + S2MPA01_REG_ID, + S2MPA01_REG_INT1, + S2MPA01_REG_INT2, + S2MPA01_REG_INT3, + S2MPA01_REG_INT1M, + S2MPA01_REG_INT2M, + S2MPA01_REG_INT3M, + S2MPA01_REG_ST1, + S2MPA01_REG_ST2, + S2MPA01_REG_PWRONSRC, + S2MPA01_REG_OFFSRC, + S2MPA01_REG_RTC_BUF, + S2MPA01_REG_CTRL1, + S2MPA01_REG_ETC_TEST, + S2MPA01_REG_RSVD1, + S2MPA01_REG_BU_CHG, + S2MPA01_REG_RAMP1, + S2MPA01_REG_RAMP2, + S2MPA01_REG_LDO_DSCH1, + S2MPA01_REG_LDO_DSCH2, + S2MPA01_REG_LDO_DSCH3, + S2MPA01_REG_LDO_DSCH4, + S2MPA01_REG_OTP_ADRL, + S2MPA01_REG_OTP_ADRH, + S2MPA01_REG_OTP_DATA, + S2MPA01_REG_MON1SEL, + S2MPA01_REG_MON2SEL, + S2MPA01_REG_LEE, + S2MPA01_REG_RSVD2, + S2MPA01_REG_RSVD3, + S2MPA01_REG_RSVD4, + S2MPA01_REG_RSVD5, + S2MPA01_REG_RSVD6, + S2MPA01_REG_TOP_RSVD, + S2MPA01_REG_DVS_SEL, + S2MPA01_REG_DVS_PTR, + S2MPA01_REG_DVS_DATA, + S2MPA01_REG_RSVD_NO, + S2MPA01_REG_UVLO, + S2MPA01_REG_LEE_NO, + S2MPA01_REG_B1CTRL1, + S2MPA01_REG_B1CTRL2, + S2MPA01_REG_B2CTRL1, + S2MPA01_REG_B2CTRL2, + S2MPA01_REG_B3CTRL1, + S2MPA01_REG_B3CTRL2, + S2MPA01_REG_B4CTRL1, + S2MPA01_REG_B4CTRL2, + S2MPA01_REG_B5CTRL1, + S2MPA01_REG_B5CTRL2, + S2MPA01_REG_B5CTRL3, + S2MPA01_REG_B5CTRL4, + S2MPA01_REG_B5CTRL5, + S2MPA01_REG_B5CTRL6, + S2MPA01_REG_B6CTRL1, + S2MPA01_REG_B6CTRL2, + S2MPA01_REG_B7CTRL1, + S2MPA01_REG_B7CTRL2, + S2MPA01_REG_B8CTRL1, + S2MPA01_REG_B8CTRL2, + S2MPA01_REG_B9CTRL1, + S2MPA01_REG_B9CTRL2, + S2MPA01_REG_B10CTRL1, + S2MPA01_REG_B10CTRL2, + S2MPA01_REG_L1CTRL, + S2MPA01_REG_L2CTRL, + S2MPA01_REG_L3CTRL, + S2MPA01_REG_L4CTRL, + S2MPA01_REG_L5CTRL, + S2MPA01_REG_L6CTRL, + S2MPA01_REG_L7CTRL, + S2MPA01_REG_L8CTRL, + S2MPA01_REG_L9CTRL, + S2MPA01_REG_L10CTRL, + S2MPA01_REG_L11CTRL, + S2MPA01_REG_L12CTRL, + S2MPA01_REG_L13CTRL, + S2MPA01_REG_L14CTRL, + S2MPA01_REG_L15CTRL, + S2MPA01_REG_L16CTRL, + S2MPA01_REG_L17CTRL, + S2MPA01_REG_L18CTRL, + S2MPA01_REG_L19CTRL, + S2MPA01_REG_L20CTRL, + S2MPA01_REG_L21CTRL, + S2MPA01_REG_L22CTRL, + S2MPA01_REG_L23CTRL, + S2MPA01_REG_L24CTRL, + S2MPA01_REG_L25CTRL, + S2MPA01_REG_L26CTRL, + + S2MPA01_REG_LDO_OVCB1, + S2MPA01_REG_LDO_OVCB2, + S2MPA01_REG_LDO_OVCB3, + S2MPA01_REG_LDO_OVCB4, + +}; + +/* S2MPA01 regulator ids */ +enum s2mpa01_regulators { + S2MPA01_LDO1, + S2MPA01_LDO2, + S2MPA01_LDO3, + S2MPA01_LDO4, + S2MPA01_LDO5, + S2MPA01_LDO6, + S2MPA01_LDO7, + S2MPA01_LDO8, + S2MPA01_LDO9, + S2MPA01_LDO10, + S2MPA01_LDO11, + S2MPA01_LDO12, + S2MPA01_LDO13, + S2MPA01_LDO14, + S2MPA01_LDO15, + S2MPA01_LDO16, + S2MPA01_LDO17, + S2MPA01_LDO18, + S2MPA01_LDO19, + S2MPA01_LDO20, + S2MPA01_LDO21, + S2MPA01_LDO22, + S2MPA01_LDO23, + S2MPA01_LDO24, + S2MPA01_LDO25, + S2MPA01_LDO26, + + S2MPA01_BUCK1, + S2MPA01_BUCK2, + S2MPA01_BUCK3, + S2MPA01_BUCK4, + S2MPA01_BUCK5, + S2MPA01_BUCK6, + S2MPA01_BUCK7, + S2MPA01_BUCK8, + S2MPA01_BUCK9, + S2MPA01_BUCK10, + + S2MPA01_REGULATOR_MAX, +}; + +#define S2MPA01_BUCK_MIN1 600000 +#define S2MPA01_BUCK_MIN2 800000 +#define S2MPA01_BUCK_MIN3 1000000 +#define S2MPA01_BUCK_MIN4 1500000 +#define S2MPA01_LDO_MIN 800000 + +#define S2MPA01_BUCK_STEP1 6250 +#define S2MPA01_BUCK_STEP2 12500 + +#define S2MPA01_LDO_STEP1 50000 +#define S2MPA01_LDO_STEP2 25000 + +#define S2MPA01_LDO_VSEL_MASK 0x3F +#define S2MPA01_BUCK_VSEL_MASK 0xFF +#define S2MPA01_ENABLE_MASK (0x03 << S2MPA01_ENABLE_SHIFT) +#define S2MPA01_ENABLE_SHIFT 0x06 +#define S2MPA01_LDO_N_VOLTAGES (S2MPA01_LDO_VSEL_MASK + 1) +#define S2MPA01_BUCK_N_VOLTAGES (S2MPA01_BUCK_VSEL_MASK + 1) + +#define S2MPA01_RAMP_DELAY 12500 /* uV/us */ + +#define S2MPA01_BUCK16_RAMP_SHIFT 4 +#define S2MPA01_BUCK24_RAMP_SHIFT 6 +#define S2MPA01_BUCK3_RAMP_SHIFT 4 +#define S2MPA01_BUCK5_RAMP_SHIFT 6 +#define S2MPA01_BUCK7_RAMP_SHIFT 2 +#define S2MPA01_BUCK8910_RAMP_SHIFT 0 + +#define S2MPA01_BUCK1_RAMP_EN_SHIFT 3 +#define S2MPA01_BUCK2_RAMP_EN_SHIFT 2 +#define S2MPA01_BUCK3_RAMP_EN_SHIFT 1 +#define S2MPA01_BUCK4_RAMP_EN_SHIFT 0 +#define S2MPA01_PMIC_EN_SHIFT 6 + +#endif /*__LINUX_MFD_S2MPA01_H */ diff --git a/include/linux/mfd/samsung/s2mps14.h b/include/linux/mfd/samsung/s2mps14.h new file mode 100644 index 000000000000..4b449b8ac548 --- /dev/null +++ b/include/linux/mfd/samsung/s2mps14.h @@ -0,0 +1,154 @@ +/* + * s2mps14.h + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_MFD_S2MPS14_H +#define __LINUX_MFD_S2MPS14_H + +/* S2MPS14 registers */ +enum s2mps14_reg { + S2MPS14_REG_ID, + S2MPS14_REG_INT1, + S2MPS14_REG_INT2, + S2MPS14_REG_INT3, + S2MPS14_REG_INT1M, + S2MPS14_REG_INT2M, + S2MPS14_REG_INT3M, + S2MPS14_REG_ST1, + S2MPS14_REG_ST2, + S2MPS14_REG_PWRONSRC, + S2MPS14_REG_OFFSRC, + S2MPS14_REG_BU_CHG, + S2MPS14_REG_RTCCTRL, + S2MPS14_REG_CTRL1, + S2MPS14_REG_CTRL2, + S2MPS14_REG_RSVD1, + S2MPS14_REG_RSVD2, + S2MPS14_REG_RSVD3, + S2MPS14_REG_RSVD4, + S2MPS14_REG_RSVD5, + S2MPS14_REG_RSVD6, + S2MPS14_REG_CTRL3, + S2MPS14_REG_RSVD7, + S2MPS14_REG_RSVD8, + S2MPS14_REG_WRSTBI, + S2MPS14_REG_B1CTRL1, + S2MPS14_REG_B1CTRL2, + S2MPS14_REG_B2CTRL1, + S2MPS14_REG_B2CTRL2, + S2MPS14_REG_B3CTRL1, + S2MPS14_REG_B3CTRL2, + S2MPS14_REG_B4CTRL1, + S2MPS14_REG_B4CTRL2, + S2MPS14_REG_B5CTRL1, + S2MPS14_REG_B5CTRL2, + S2MPS14_REG_L1CTRL, + S2MPS14_REG_L2CTRL, + S2MPS14_REG_L3CTRL, + S2MPS14_REG_L4CTRL, + S2MPS14_REG_L5CTRL, + S2MPS14_REG_L6CTRL, + S2MPS14_REG_L7CTRL, + S2MPS14_REG_L8CTRL, + S2MPS14_REG_L9CTRL, + S2MPS14_REG_L10CTRL, + S2MPS14_REG_L11CTRL, + S2MPS14_REG_L12CTRL, + S2MPS14_REG_L13CTRL, + S2MPS14_REG_L14CTRL, + S2MPS14_REG_L15CTRL, + S2MPS14_REG_L16CTRL, + S2MPS14_REG_L17CTRL, + S2MPS14_REG_L18CTRL, + S2MPS14_REG_L19CTRL, + S2MPS14_REG_L20CTRL, + S2MPS14_REG_L21CTRL, + S2MPS14_REG_L22CTRL, + S2MPS14_REG_L23CTRL, + S2MPS14_REG_L24CTRL, + S2MPS14_REG_L25CTRL, + S2MPS14_REG_LDODSCH1, + S2MPS14_REG_LDODSCH2, + S2MPS14_REG_LDODSCH3, +}; + +/* S2MPS14 regulator ids */ +enum s2mps14_regulators { + S2MPS14_LDO1, + S2MPS14_LDO2, + S2MPS14_LDO3, + S2MPS14_LDO4, + S2MPS14_LDO5, + S2MPS14_LDO6, + S2MPS14_LDO7, + S2MPS14_LDO8, + S2MPS14_LDO9, + S2MPS14_LDO10, + S2MPS14_LDO11, + S2MPS14_LDO12, + S2MPS14_LDO13, + S2MPS14_LDO14, + S2MPS14_LDO15, + S2MPS14_LDO16, + S2MPS14_LDO17, + S2MPS14_LDO18, + S2MPS14_LDO19, + S2MPS14_LDO20, + S2MPS14_LDO21, + S2MPS14_LDO22, + S2MPS14_LDO23, + S2MPS14_LDO24, + S2MPS14_LDO25, + S2MPS14_BUCK1, + S2MPS14_BUCK2, + S2MPS14_BUCK3, + S2MPS14_BUCK4, + S2MPS14_BUCK5, + + S2MPS14_REGULATOR_MAX, +}; + +/* Regulator constraints for BUCKx */ +#define S2MPS14_BUCK1235_MIN_600MV 600000 +#define S2MPS14_BUCK4_MIN_1400MV 1400000 +#define S2MPS14_BUCK1235_STEP_6_25MV 6250 +#define S2MPS14_BUCK4_STEP_12_5MV 12500 +#define S2MPS14_BUCK1235_START_SEL 0x20 +#define S2MPS14_BUCK4_START_SEL 0x40 +/* + * Default ramp delay in uv/us. Datasheet says that ramp delay can be + * controlled however it does not specify which register is used for that. + * Let's assume that default value will be set. + */ +#define S2MPS14_BUCK_RAMP_DELAY 12500 + +/* Regulator constraints for different types of LDOx */ +#define S2MPS14_LDO_MIN_800MV 800000 +#define S2MPS14_LDO_MIN_1800MV 1800000 +#define S2MPS14_LDO_STEP_12_5MV 12500 +#define S2MPS14_LDO_STEP_25MV 25000 + +#define S2MPS14_LDO_VSEL_MASK 0x3F +#define S2MPS14_BUCK_VSEL_MASK 0xFF +#define S2MPS14_ENABLE_MASK (0x03 << S2MPS14_ENABLE_SHIFT) +#define S2MPS14_ENABLE_SHIFT 6 +/* On/Off controlled by PWREN */ +#define S2MPS14_ENABLE_SUSPEND (0x01 << S2MPS14_ENABLE_SHIFT) +#define S2MPS14_LDO_N_VOLTAGES (S2MPS14_LDO_VSEL_MASK + 1) +#define S2MPS14_BUCK_N_VOLTAGES (S2MPS14_BUCK_VSEL_MASK + 1) + +#endif /* __LINUX_MFD_S2MPS14_H */ diff --git a/include/linux/mfd/samsung/s5m8767.h b/include/linux/mfd/samsung/s5m8767.h index 306a95fc558c..243b58fec33d 100644 --- a/include/linux/mfd/samsung/s5m8767.h +++ b/include/linux/mfd/samsung/s5m8767.h @@ -183,6 +183,29 @@ enum s5m8767_regulators { S5M8767_REG_MAX, }; -#define S5M8767_ENCTRL_SHIFT 6 +/* LDO_EN/BUCK_EN field in registers */ +#define S5M8767_ENCTRL_SHIFT 6 +#define S5M8767_ENCTRL_MASK (0x3 << S5M8767_ENCTRL_SHIFT) + +/* + * LDO_EN/BUCK_EN register value for controlling this Buck or LDO + * by GPIO (PWREN, BUCKEN). + */ +#define S5M8767_ENCTRL_USE_GPIO 0x1 + +/* + * Values for BUCK_RAMP field in DVS_RAMP register, matching raw values + * in mV/us. + */ +enum s5m8767_dvs_buck_ramp_values { + S5M8767_DVS_BUCK_RAMP_5 = 0x4, + S5M8767_DVS_BUCK_RAMP_10 = 0x9, + S5M8767_DVS_BUCK_RAMP_12_5 = 0xb, + S5M8767_DVS_BUCK_RAMP_25 = 0xd, + S5M8767_DVS_BUCK_RAMP_50 = 0xe, + S5M8767_DVS_BUCK_RAMP_100 = 0xf, +}; +#define S5M8767_DVS_BUCK_RAMP_SHIFT 4 +#define S5M8767_DVS_BUCK_RAMP_MASK (0xf << S5M8767_DVS_BUCK_RAMP_SHIFT) #endif /* __LINUX_MFD_S5M8767_H */ diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index b6d36b38b99c..ff44374a1a4e 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -212,6 +212,7 @@ #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4) #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4) +#define IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT 2 #define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2) #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2) #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2) @@ -241,6 +242,24 @@ #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) +#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) +#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK (0xf << 8) +#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK (0xf << 12) +#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK (0xf << 16) +#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK (0xf << 20) +#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24) +#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK (0xf << 28) + +#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK (0xf << 0) +#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK (0xf << 4) +#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK (0xf << 8) +#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK (0xf << 12) +#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK (0xf << 16) +#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK (0xf << 20) +#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24) +#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28) + #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) #define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h index d498d98f0c2c..fb96c84dada5 100644 --- a/include/linux/mfd/ti_am335x_tscadc.h +++ b/include/linux/mfd/ti_am335x_tscadc.h @@ -159,6 +159,9 @@ struct ti_tscadc_dev { int adc_cell; /* -1 if not used */ struct mfd_cell cells[TSCADC_CELLS]; u32 reg_se_cache; + bool adc_waiting; + bool adc_in_use; + wait_queue_head_t reg_se_wait; spinlock_t reg_lock; unsigned int clk_div; @@ -176,8 +179,9 @@ static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p) return *tscadc_dev; } -void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc); -void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val); +void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val); +void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val); void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val); +void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc); #endif diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h index b22883d60500..8f6f2e91e7ae 100644 --- a/include/linux/mfd/tmio.h +++ b/include/linux/mfd/tmio.h @@ -76,6 +76,13 @@ */ #define TMIO_MMC_USE_GPIO_CD (1 << 5) +/* + * Some controllers doesn't have over 0x100 register. + * it is used to checking accessibility of + * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL + */ +#define TMIO_MMC_HAVE_HIGH_REG (1 << 6) + int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); @@ -102,6 +109,7 @@ struct tmio_mmc_data { unsigned long capabilities; unsigned long capabilities2; unsigned long flags; + unsigned long bus_shift; u32 ocr_mask; /* available voltages */ struct tmio_mmc_dma *dma; struct device *dev; diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h index a5a7f0130e96..54b5458ec084 100644 --- a/include/linux/mfd/tps65217.h +++ b/include/linux/mfd/tps65217.h @@ -252,7 +252,7 @@ struct tps65217_board { struct tps65217 { struct device *dev; struct tps65217_board *pdata; - unsigned int id; + unsigned long id; struct regulator_desc desc[TPS65217_NUM_REGULATOR]; struct regulator_dev *rdev[TPS65217_NUM_REGULATOR]; struct regmap *regmap; @@ -263,7 +263,7 @@ static inline struct tps65217 *dev_to_tps65217(struct device *dev) return dev_get_drvdata(dev); } -static inline int tps65217_chip_id(struct tps65217 *tps65217) +static inline unsigned long tps65217_chip_id(struct tps65217 *tps65217) { return tps65217->id; } diff --git a/include/linux/mfd/tps65218.h b/include/linux/mfd/tps65218.h new file mode 100644 index 000000000000..d2e357df5a0e --- /dev/null +++ b/include/linux/mfd/tps65218.h @@ -0,0 +1,284 @@ +/* + * linux/mfd/tps65218.h + * + * Functions to access TPS65219 power management chip. + * + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + */ + +#ifndef __LINUX_MFD_TPS65218_H +#define __LINUX_MFD_TPS65218_H + +#include <linux/i2c.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/bitops.h> + +/* TPS chip id list */ +#define TPS65218 0xF0 + +/* I2C ID for TPS65218 part */ +#define TPS65218_I2C_ID 0x24 + +/* All register addresses */ +#define TPS65218_REG_CHIPID 0x00 +#define TPS65218_REG_INT1 0x01 +#define TPS65218_REG_INT2 0x02 +#define TPS65218_REG_INT_MASK1 0x03 +#define TPS65218_REG_INT_MASK2 0x04 +#define TPS65218_REG_STATUS 0x05 +#define TPS65218_REG_CONTROL 0x06 +#define TPS65218_REG_FLAG 0x07 + +#define TPS65218_REG_PASSWORD 0x10 +#define TPS65218_REG_ENABLE1 0x11 +#define TPS65218_REG_ENABLE2 0x12 +#define TPS65218_REG_CONFIG1 0x13 +#define TPS65218_REG_CONFIG2 0x14 +#define TPS65218_REG_CONFIG3 0x15 +#define TPS65218_REG_CONTROL_DCDC1 0x16 +#define TPS65218_REG_CONTROL_DCDC2 0x17 +#define TPS65218_REG_CONTROL_DCDC3 0x18 +#define TPS65218_REG_CONTROL_DCDC4 0x19 +#define TPS65218_REG_CONTRL_SLEW_RATE 0x1A +#define TPS65218_REG_CONTROL_LDO1 0x1B +#define TPS65218_REG_SEQ1 0x20 +#define TPS65218_REG_SEQ2 0x21 +#define TPS65218_REG_SEQ3 0x22 +#define TPS65218_REG_SEQ4 0x23 +#define TPS65218_REG_SEQ5 0x24 +#define TPS65218_REG_SEQ6 0x25 +#define TPS65218_REG_SEQ7 0x26 + +/* Register field definitions */ +#define TPS65218_CHIPID_CHIP_MASK 0xF8 +#define TPS65218_CHIPID_REV_MASK 0x07 + +#define TPS65218_INT1_VPRG BIT(5) +#define TPS65218_INT1_AC BIT(4) +#define TPS65218_INT1_PB BIT(3) +#define TPS65218_INT1_HOT BIT(2) +#define TPS65218_INT1_CC_AQC BIT(1) +#define TPS65218_INT1_PRGC BIT(0) + +#define TPS65218_INT2_LS3_F BIT(5) +#define TPS65218_INT2_LS2_F BIT(4) +#define TPS65218_INT2_LS1_F BIT(3) +#define TPS65218_INT2_LS3_I BIT(2) +#define TPS65218_INT2_LS2_I BIT(1) +#define TPS65218_INT2_LS1_I BIT(0) + +#define TPS65218_INT_MASK1_VPRG BIT(5) +#define TPS65218_INT_MASK1_AC BIT(4) +#define TPS65218_INT_MASK1_PB BIT(3) +#define TPS65218_INT_MASK1_HOT BIT(2) +#define TPS65218_INT_MASK1_CC_AQC BIT(1) +#define TPS65218_INT_MASK1_PRGC BIT(0) + +#define TPS65218_INT_MASK2_LS3_F BIT(5) +#define TPS65218_INT_MASK2_LS2_F BIT(4) +#define TPS65218_INT_MASK2_LS1_F BIT(3) +#define TPS65218_INT_MASK2_LS3_I BIT(2) +#define TPS65218_INT_MASK2_LS2_I BIT(1) +#define TPS65218_INT_MASK2_LS1_I BIT(0) + +#define TPS65218_STATUS_FSEAL BIT(7) +#define TPS65218_STATUS_EE BIT(6) +#define TPS65218_STATUS_AC_STATE BIT(5) +#define TPS65218_STATUS_PB_STATE BIT(4) +#define TPS65218_STATUS_STATE_MASK 0xC +#define TPS65218_STATUS_CC_STAT 0x3 + +#define TPS65218_CONTROL_OFFNPFO BIT(1) +#define TPS65218_CONTROL_CC_AQ BIT(0) + +#define TPS65218_FLAG_GPO3_FLG BIT(7) +#define TPS65218_FLAG_GPO2_FLG BIT(6) +#define TPS65218_FLAG_GPO1_FLG BIT(5) +#define TPS65218_FLAG_LDO1_FLG BIT(4) +#define TPS65218_FLAG_DC4_FLG BIT(3) +#define TPS65218_FLAG_DC3_FLG BIT(2) +#define TPS65218_FLAG_DC2_FLG BIT(1) +#define TPS65218_FLAG_DC1_FLG BIT(0) + +#define TPS65218_ENABLE1_DC6_EN BIT(5) +#define TPS65218_ENABLE1_DC5_EN BIT(4) +#define TPS65218_ENABLE1_DC4_EN BIT(3) +#define TPS65218_ENABLE1_DC3_EN BIT(2) +#define TPS65218_ENABLE1_DC2_EN BIT(1) +#define TPS65218_ENABLE1_DC1_EN BIT(0) + +#define TPS65218_ENABLE2_GPIO3 BIT(6) +#define TPS65218_ENABLE2_GPIO2 BIT(5) +#define TPS65218_ENABLE2_GPIO1 BIT(4) +#define TPS65218_ENABLE2_LS3_EN BIT(3) +#define TPS65218_ENABLE2_LS2_EN BIT(2) +#define TPS65218_ENABLE2_LS1_EN BIT(1) +#define TPS65218_ENABLE2_LDO1_EN BIT(0) + + +#define TPS65218_CONFIG1_TRST BIT(7) +#define TPS65218_CONFIG1_GPO2_BUF BIT(6) +#define TPS65218_CONFIG1_IO1_SEL BIT(5) +#define TPS65218_CONFIG1_PGDLY_MASK 0x18 +#define TPS65218_CONFIG1_STRICT BIT(2) +#define TPS65218_CONFIG1_UVLO_MASK 0x3 + +#define TPS65218_CONFIG2_DC12_RST BIT(7) +#define TPS65218_CONFIG2_UVLOHYS BIT(6) +#define TPS65218_CONFIG2_LS3ILIM_MASK 0xC +#define TPS65218_CONFIG2_LS2ILIM_MASK 0x3 + +#define TPS65218_CONFIG3_LS3NPFO BIT(5) +#define TPS65218_CONFIG3_LS2NPFO BIT(4) +#define TPS65218_CONFIG3_LS1NPFO BIT(3) +#define TPS65218_CONFIG3_LS3DCHRG BIT(2) +#define TPS65218_CONFIG3_LS2DCHRG BIT(1) +#define TPS65218_CONFIG3_LS1DCHRG BIT(0) + +#define TPS65218_CONTROL_DCDC1_PFM BIT(7) +#define TPS65218_CONTROL_DCDC1_MASK 0x7F + +#define TPS65218_CONTROL_DCDC2_PFM BIT(7) +#define TPS65218_CONTROL_DCDC2_MASK 0x3F + +#define TPS65218_CONTROL_DCDC3_PFM BIT(7) +#define TPS65218_CONTROL_DCDC3_MASK 0x3F + +#define TPS65218_CONTROL_DCDC4_PFM BIT(7) +#define TPS65218_CONTROL_DCDC4_MASK 0x3F + +#define TPS65218_SLEW_RATE_GO BIT(7) +#define TPS65218_SLEW_RATE_GODSBL BIT(6) +#define TPS65218_SLEW_RATE_SLEW_MASK 0x7 + +#define TPS65218_CONTROL_LDO1_MASK 0x3F + +#define TPS65218_SEQ1_DLY8 BIT(7) +#define TPS65218_SEQ1_DLY7 BIT(6) +#define TPS65218_SEQ1_DLY6 BIT(5) +#define TPS65218_SEQ1_DLY5 BIT(4) +#define TPS65218_SEQ1_DLY4 BIT(3) +#define TPS65218_SEQ1_DLY3 BIT(2) +#define TPS65218_SEQ1_DLY2 BIT(1) +#define TPS65218_SEQ1_DLY1 BIT(0) + +#define TPS65218_SEQ2_DLYFCTR BIT(7) +#define TPS65218_SEQ2_DLY9 BIT(0) + +#define TPS65218_SEQ3_DC2_SEQ_MASK 0xF0 +#define TPS65218_SEQ3_DC1_SEQ_MASK 0xF + +#define TPS65218_SEQ4_DC4_SEQ_MASK 0xF0 +#define TPS65218_SEQ4_DC3_SEQ_MASK 0xF + +#define TPS65218_SEQ5_DC6_SEQ_MASK 0xF0 +#define TPS65218_SEQ5_DC5_SEQ_MASK 0xF + +#define TPS65218_SEQ6_LS1_SEQ_MASK 0xF0 +#define TPS65218_SEQ6_LDO1_SEQ_MASK 0xF + +#define TPS65218_SEQ7_GPO3_SEQ_MASK 0xF0 +#define TPS65218_SEQ7_GPO1_SEQ_MASK 0xF +#define TPS65218_PROTECT_NONE 0 +#define TPS65218_PROTECT_L1 1 + +enum tps65218_regulator_id { + /* DCDC's */ + TPS65218_DCDC_1, + TPS65218_DCDC_2, + TPS65218_DCDC_3, + TPS65218_DCDC_4, + TPS65218_DCDC_5, + TPS65218_DCDC_6, + /* LDOs */ + TPS65218_LDO_1, +}; + +#define TPS65218_MAX_REG_ID TPS65218_LDO_1 + +/* Number of step-down converters available */ +#define TPS65218_NUM_DCDC 6 +/* Number of LDO voltage regulators available */ +#define TPS65218_NUM_LDO 1 +/* Number of total regulators available */ +#define TPS65218_NUM_REGULATOR (TPS65218_NUM_DCDC + TPS65218_NUM_LDO) + +/* Define the TPS65218 IRQ numbers */ +enum tps65218_irqs { + /* INT1 registers */ + TPS65218_PRGC_IRQ, + TPS65218_CC_AQC_IRQ, + TPS65218_HOT_IRQ, + TPS65218_PB_IRQ, + TPS65218_AC_IRQ, + TPS65218_VPRG_IRQ, + TPS65218_INVALID1_IRQ, + TPS65218_INVALID2_IRQ, + /* INT2 registers */ + TPS65218_LS1_I_IRQ, + TPS65218_LS2_I_IRQ, + TPS65218_LS3_I_IRQ, + TPS65218_LS1_F_IRQ, + TPS65218_LS2_F_IRQ, + TPS65218_LS3_F_IRQ, + TPS65218_INVALID3_IRQ, + TPS65218_INVALID4_IRQ, +}; + +/** + * struct tps_info - packages regulator constraints + * @id: Id of the regulator + * @name: Voltage regulator name + * @min_uV: minimum micro volts + * @max_uV: minimum micro volts + * + * This data is used to check the regualtor voltage limits while setting. + */ +struct tps_info { + int id; + const char *name; + int min_uV; + int max_uV; +}; + +/** + * struct tps65218 - tps65218 sub-driver chip access routines + * + * Device data may be used to access the TPS65218 chip + */ + +struct tps65218 { + struct device *dev; + unsigned int id; + + struct mutex tps_lock; /* lock guarding the data structure */ + /* IRQ Data */ + int irq; + u32 irq_mask; + struct regmap_irq_chip_data *irq_data; + struct regulator_desc desc[TPS65218_NUM_REGULATOR]; + struct regulator_dev *rdev[TPS65218_NUM_REGULATOR]; + struct tps_info *info[TPS65218_NUM_REGULATOR]; + struct regmap *regmap; +}; + +int tps65218_reg_read(struct tps65218 *tps, unsigned int reg, + unsigned int *val); +int tps65218_reg_write(struct tps65218 *tps, unsigned int reg, + unsigned int val, unsigned int level); +int tps65218_set_bits(struct tps65218 *tps, unsigned int reg, + unsigned int mask, unsigned int val, unsigned int level); +int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, + unsigned int mask, unsigned int level); + +#endif /* __LINUX_MFD_TPS65218_H */ diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h index 87994542573b..cbecec2e353a 100644 --- a/include/linux/mfd/tps6586x.h +++ b/include/linux/mfd/tps6586x.h @@ -13,6 +13,12 @@ #define TPS6586X_SLEW_RATE_SET 0x08 #define TPS6586X_SLEW_RATE_MASK 0x07 +/* VERSION CRC */ +#define TPS658621A 0x15 +#define TPS658621CD 0x2c +#define TPS658623 0x1b +#define TPS658643 0x03 + enum { TPS6586X_ID_SYS, TPS6586X_ID_SM_0, @@ -97,5 +103,6 @@ extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); extern int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask); extern int tps6586x_irq_get_virq(struct device *dev, int irq); +extern int tps6586x_get_version(struct device *dev); #endif /*__LINUX_MFD_TPS6586X_H */ diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 20e433e551e3..16c2335c2856 100644 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -358,8 +358,6 @@ /*Register BBCH (0x80) register.RegisterDescription */ #define BBCH_BBSEL_MASK 0x06 #define BBCH_BBSEL_SHIFT 1 -#define BBCH_BBCHEN_MASK 0x01 -#define BBCH_BBCHEN_SHIFT 0 /*Register DCDCCTRL (0x80) register.RegisterDescription */ @@ -833,6 +831,7 @@ #define TPS65910_REG_VAUX2 10 #define TPS65910_REG_VAUX33 11 #define TPS65910_REG_VMMC 12 +#define TPS65910_REG_VBB 13 #define TPS65911_REG_VDDCTRL 4 #define TPS65911_REG_LDO1 5 @@ -845,7 +844,7 @@ #define TPS65911_REG_LDO8 12 /* Max number of TPS65910/11 regulators */ -#define TPS65910_NUM_REGS 13 +#define TPS65910_NUM_REGS 14 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ #define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1 |