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| author | Bjorn Helgaas <bhelgaas@google.com> | 2013-08-27 09:54:40 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-11-29 10:42:15 -0800 |
| commit | 850bf53b5219291b9c4543d8a69d2cd9a4908153 (patch) | |
| tree | 38d3d5213c250faa48b2e5f984dba50f2ecc8626 /tools/perf/scripts/python | |
| parent | f484c09fbbdf2c97175ab7f08ab713e5d88ff99f (diff) | |
PCI: Allow PCIe Capability link-related register access for switches
commit d3694d4fa3f44f6a295f8ab064937c8a1549d174 upstream.
Every PCIe device has a link, except Root Complex Integrated Endpoints
and Root Complex Event Collectors. Previously we didn't give access
to PCIe capability link-related registers for Upstream Ports, Downstream
Ports, and Bridges, so attempts to read PCI_EXP_LNKCTL incorrectly
returned zero. See PCIe spec r3.0, sec 7.8 and 1.3.2.3.
Reference: http://lkml.kernel.org/r/979A8436335E3744ADCD3A9F2A2B68A52AD136BE@SJEXCHMB10.corp.ad.broadcom.com
Reported-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions