diff options
| author | Claudiu Manoil <claudiu.manoil@nxp.com> | 2026-01-30 16:10:32 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-02-11 13:41:57 +0100 |
| commit | d98745c68023f8a45a4f5d7299b83994ee96213c (patch) | |
| tree | afb5c889308d11f677e6913dbd8995cbc509219e /scripts/basic/split-include.c | |
| parent | c175b1eaf729eb9f5694cdfc7814fa8ad90e63e7 (diff) | |
net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4
[ Upstream commit a69c17230cab07bd156f894fdc82bd78b43ea72f ]
For ENETC v4 these settings are controlled by the global ENETC
message and buffer cache attribute registers (EnBCAR and EnMCAR),
from the IERB register block.
The hardcoded cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.
Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Link: https://patch.msgid.link/20260130141035.272471-2-claudiu.manoil@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions